View ISL94202EVKIT1Z_9016750.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fn8889 rev.2.00 page 1 of 89 mar 8, 2017 fn8889 rev.2.00 mar 8, 2017 isl94202 series charge/discharge path 3-to-8 cell li-ion battery pack mo nitor datasheet 1. overview the isl94202 is a li-ion battery monitor ic that supports from three to eig ht series connected cells . it provides complete battery monitoring and pack control. the isl94202 provides auto matic shutdown and recovery from out-of-bounds conditions and automatically control s pack cell balancing. the isl94202 is highly configurab le as a stand-al one unit, but can be used with an extern al microcontroller, which communicates to the ic through an i 2 c interface. 1.1 features ? eight cell voltage monitors support li-ion coo 2 , li-ion mn 2 o 4 , and li-ion fepo 4 chemistries ? stand-alone pack control - no microcontroller needed ? multiple voltage pro tection options (each p rogrammable to 4.8v ; 12-bit digital value) and selectab le overcurrent p rotection le vels ? programmable detection/recovery times for overvoltage, undervo ltage, overcurrent, and short-circuit conditions ? configuration/calibration registers maintained in eeprom ? open battery connect detection ? integrated charge/discharge fet drive circuitry with built-in charge pump supports high-side n-channel fets ? cell balancing uses external fe ts with internal state machine or external microcontroller ? enters low power states a fter periods of inactivity ? charge or discharge current det ection resumes normal scan rate s 1.2 applications ? power tools ? battery back-up systems ? light electric vehicles ? portable equipment ? energy storage systems ? solar farms ? medical equipment ? hospital beds ? monitoring equipment ? ventilators 1.3 related literature ? for a full list of related documents, visit our website ? isl94202 product page
isl94202 1. overview fn8889 rev.2.00 page 2 of 89 mar 8, 2017 1.4 typical application diagram gnd chrg p+ p- vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 isl94202 vss cs1 cs2 cfet pcfet vdd dfet ldmon chmon vbatt rgo vref scl sda sd eoc int fetsoff psd tempo xt1 xt2 addr c2 c3 c1 43v 43v figure 1.1 typical ap plication diagram
isl94202 1. overview fn8889 rev.2.00 page 3 of 89 mar 8, 2017 1.5 block diagram osc p+ p- 1k ? 1k ? 1k? 47nf 47nf 47nf 1k ? 47nf 1k? 47nf 47nf 1k ? 47nf 1k ? cs1 cs2 ram eeprom sd vss eoc vss pack- pack+ bat+ bat- vb/16 rgo/2 cb1 cb2 cb3 cb4 cb5 cb6 cb7 rgo 1k? 47nf cb8 fet controls/charge pump cfet dfet ldmon o.c. recovery wakeup circuit n-channel fets vdd sdai scl fetsoff tempo registers addr sdao xt2 xt1 input buffer/level shifter/open wire detect vc6 vc3 vc4 vc5 vc7 vc1 vc2 vc0 vc8 rgo (out) reg ldo current-sense gain amplifier x5/x50/x500 gain chmon cb state cb8:1 pcfet i 2 c power-on machine reset state machine timing and control memory manager scan state cb state overcurrent state eoc /sd /error state temp/voltage monitor alu overcurrent state machine vdd vdd psd v ss c1 c2 c3 vref vref int vbatt 100 ? 470nf mux mux xt2 xt1 temp 14-bit scan state machine +16v +16v adc 330k ? 10k ? 330k ? 10k ? 330k ? 10k ? 10k ? 10k ? 10k ? 10k ? 10k ? 330k ? 330k ? 330k ? 330k ? 330k ? eoc /sd error conditions (ov, uv, slp state machines) watchdog timer it temp t gain mux x1/x2 figure 1.2 block diagram
isl94202 1. overview fn8889 rev.2.00 page 4 of 89 mar 8, 2017 1.6 ordering information part number ( notes 1 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # isl94202irtz 94202 irtz -40 to +85 48 ld tqfn l48.6x6 ISL94202EVKIT1Z evaluation kit notes: 1. add -t suffix for 4k unit, -t7 for 1k unit, or -t7a suf fix for 250 unit tape and reel options. refer to tb347 for details on reel specifications. 2. these intersil pb-free plasti c packaged products employ speci al pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free produc ts are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), see product information page for isl94202 . for more information on msl, see tech brief tb363 . table 1.1 key differences between family of parts part # cells supported pack voltage (op) cell balance current sense charge/discharge fet supply current (typ) stand- alone capable internal adc daisy chain min max min (v) max (v) control arrangement location normal sleep isl94202 3 8 4 36 external high side yes one path high side 348a 13a yes yes no isl94203 3 8 4 36 external high side yes two path high side 348a 13a yes yes no isl94208 4 6 8 26.4 internal low side yes both low side 850a 2a no no no isl94212 6 12 6 60 external no no n/a n/a 3.31ma 12a no yes yes
isl94202 1. overview fn8889 rev.2.00 page 5 of 89 mar 8, 2017 1.7 pin configuration isl94202 (48 ld tqfn) top view vbatt csi1 csi2 cfet 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 pcfet vdd dfet c1 c2 c3 ldmon chmon vc2 cb2 vc1 cb1 vc0 vss vref xt1 xt2 tempo dnc addr vss rgo eoc sd fetsoff psd int dnc vss sdao sdai scl vc8 cb8 vc7 cb7 vc6 cb6 vc5 cb5 vc4 cb4 vc3 cb3 pad (gnd)
isl94202 1. overview fn8889 rev.2.00 page 6 of 89 mar 8, 2017 1.8 pin descriptions pin number symbol description 1, 3, 5, 7, 9, 11, 13, 15, 17 vc[8:0] battery cell n voltage input. this pin is used to monitor the voltage of this battery cell. t he voltage is level shifted to a ground reference and is monitored internally by an adc converter. vcn connects to the positive terminal of a battery cell (celln) and vc(n-1) the negative ter minal of celln (vss connects with the negative terminal of cell1). 2, 4, 6, 8, 10, 12, 14, 16 cb[8:1] cell balancing fet control output n. this internal drive c ircuit controls an ex ternal fet used to d ivert a portion of the current around a cell while the cell is being ch arged or adds to the current pulled from a cell during discharge in order to perfo rm a cell voltage balancing o peration. this function is generally used to reduce the voltage on an individual cell relative to other cell s in the pack. the cell balancing fets are turned on or off by an internal cell balance state machine or an exter nal controller. 18, 28, 29 vss ground . this pin connects to the most negative terminal in the battery string. 19 vref voltage reference output. this output provides a 1.8v reference voltage for the internal circuitry and for the external microcontroller. 20 xt1 temperature monitor inputs. these pins input the voltage across two external thermistors used to determine the temperature of the cells and or the power fet. when this in put drops below the threshold, an external over-temperature condition exists. 21 xt2 22 tempo temperature monitor output control. this pin outputs a voltage to be used in a divider that consist s of a fixed resistor and a thermistor. the thermistor is located in c lose proximity to the cells or the power fet. the tempo output is connected internally to the vref voltage throug h a pmos switch only during a measurement of the temperature, otherwise the tempo output is off. 23, 30 dnc do not connect 24 addr serial address. this is an address input for an i 2 c communication link to allow for two devices on one bus. 25 scl serial clock. this is the clock input for an i 2 c communication link. 26 sdai serial data. these are the data lines for an i 2 c interface. when connected together, they form the standard bidirectional interface for the i 2 c bus (recommended). when separated, they can use separate leve l shifters for two-device operation (not supported). 27 sdao 31 int interrupt. this pin goes active low when t here is an external c connecte d to the isl94202 and c communication fails to send a sl ave byte within a watchdog time r period. this is a cmos type output. 32 psd pack shutdown. this pin goes active high when any cell voltage reaches the ov lo threshold (ovlo flag). optionally, psd is also set if there is a voltage differential between any two cells that is greater than a specified limit (cellf flag) or if there is an open-wire condition. this pin can be used for blowing a fuse in the pack or as an interrupt to an external c. 33 fetsoff fetsoff. this input allows an external microcontroller to turn off both power fet and cb outputs. this pin should be pulled low when inactive. 34 sd shutdown. this output indicates that the isl94202 detected any failure condition that would result in the dfet turning off. this could be undervoltage, overcurrent, over -temperature, under-temperature, etc. the sd pin also goes active if there is any charge overcurrent condition. this is an open-drain output. 35 eoc end-of-charge. this output indicates that the isl94202 detected a fully charged condition. this is defined by any cell voltage exceeding an eoc voltage (as defined by an eoc value in eeprom). 36 rgo regulator output. this is the 2.5v regulator output. 37 chmon charge monitor. this input monitors the charger connection. when the ic is in the sleep mode, connecting this pin to the charger wakes up the device. when the ic recove rs from a charge overcurrent condition, this pin is used to monitor that the charger is removed prior to turning on the power fets. in a single-path configuration, this pin and t he ldmon pin connect together. 38 ldmon load monitor. this pin monitors the load connection. when the ic is in the sl eep mode, connecting this pin to a load wakes up the device. when the ic recovers from a dischar ge overcurrent or short-circuit condition, this pin is used to monitor that the load is removed prior to turnin g on the power fets. in a single path configuration, this pin and t he chmon pin connect together. 39, 40, 41 c[3:1] charge pump capacitor pins. these external capacitors are used for the charge pump driving the power fets. 42 dfet discharge fet control. the isl94202 controls the gate of a discharge fet through this pin. the power fet is an n-channel device. the fet is turned on by the isl94202 if all conditions are acceptable. the isl94202 will turn off the fet in the event of an out-of-bounds conditio n. the fet can be turned off by an external microcontroller by writing to the cfet control bit. the cfet ou tput is also turned off by the fetsoff pin. the fet output cannot be turned on by an external microcontroller i f there are any out-of-bounds conditions. 43 vdd ic supply pin. this pin provides the operating voltage for the ic circuitry.
isl94202 1. overview fn8889 rev.2.00 page 7 of 89 mar 8, 2017 44 pcfet precharge fet control. the isl94202 controls the gate of a precharge fet through this pin. the power fet is an n-channel device. the fet is turned on by the isl94202 if all conditions are acceptable. the isl94202 will turn off the fet in the event of an out-of-bounds conditio n. the fet can be turned off by an external microcontroller by writing to the pcfet control bit. the pcfet output is also turned off by the fetsoff pin. the fet output cannot be turned on by an external microcontroll er if there are any out-of-bounds conditions. either the pcfet or the cfet turn on, but not both. 45 cfet charge fet control. the isl94202 controls the gate of a charge fet through this pi n. the power fet is an n-channel device. the fet is tu rned on by the isl94202 if all conditions are acceptable. the isl 94202 will t urn off the fet in the event of an out-of-bounds condition. th e fet can be turned off by an external microcontroller by writing to the cfet control bit. the cfet ou tput is also turned off by the fetsoff pin. the fet output cannot be turned on by an external microcontroller i f there are any out-of-bounds conditions. either the pcfet or the cfet turn on, but not both. 46 csi2 current-sense inputs. these pins connect to the isl94202 current-sense circuit. ther e is an external resistance across which the circ uit operates. the sense resisto r is typically in the range of 0.2m to 5m. 47 csi1 48 vbatt input level shifter supply and battery pack voltage input. this pin powers the input level shifters and is also used to monitor the voltage of the battery stack. the volt age is internally divided by 32 and connected to an adc converter through a mux. pad gnd thermal pad. this pad should connect to ground. pin number symbol description
fn8889 rev.2.00 page 8 of 89 mar 8, 2017 isl94202 contents 1. overview ......... .............................. ............................ ................................. ........... 1 1.1 features ................................................... ................................................................................. 1 1.2 applications ............................................... ............................................................................... 1 1.3 related literature ......................................... ............................................................................ 1 1.4 typical application diagram ................................ ..................................................................... 2 1.5 block diagram .............................................. ............................................................................ 3 1.6 ordering information ....................................... .......................................................................... 4 1.7 pin configuration .......................................... ............................................................................ 5 1.8 pin descriptions ........................................... ............................................................................. 6 3. specifications ............................................................................................. ......... 11 3.1 absolute maximum ratings ................................... ............................................................... .. 11 3.2 thermal information ........................................ ............................................................... ......... 12 3.3 recommended operating conditions ........................... .......................................................... 12 3.4 electrical specification ................................... ............................................................... .......... 13 3.5 symbol table ............................................... ............................................................... ............ 20 3.6 timing diagrams ............................................ ............................................................... .......... 20 3.6.1 external temperature configuration ....................... ............................................................ 20 3.6.2 wake-up timing .......................................... ............................................................... ....... 21 3.6.3 power-up timing .......................................... ............................................................... ....... 21 3.6.4 change in fet control .................................... ............................................................... .... 22 3.6.5 automatic temperature scan ............................... .............................................................. 23 3.6.6 serial interface timing diagrams ......................... .............................................................. 23 3.6.7 discharge overcurrent/sho rt-circuit monitor .............. ........................................................ 24 3.6.8 charge overcurrent moni tor ............................... ............................................................... . 24 4. functional description ....... ................ ............... ......................................... ......... 25 5. battery connections .......................... ............... ......................................... ......... 26 5.1 power path ................................................. ............................................................... ............. 26 5.2 pack configuration ......................................... ............................................................... ......... 27 5.3 battery cell connections ................................... ............................................................... ...... 27 6. operating modes ............ ........................................................................... ......... 28 6.1 power-up operation ......................................... ............................................................... ....... 28 6.2 wake-up circuit ............................................ ............................................................... ........... 29 6.3 low power states ........................................... ............................................................... ......... 30 6.3.1 normal mode .............................................. ............................................................... ......... 30 6.3.2 idle mode ................................................ ............................................................... ............. 30 6.3.3 doze mode ................................................ ............................................................... .......... 30 6.3.4 sleep mode ............................................... ............................................................... ........... 30 6.3.5 power-down mode .......................................... ............................................................... .... 31 6.3.6 exceptions ............................................... ............................................................... ............ 31
fn8889 rev.2.00 page 9 of 89 mar 8, 2017 isl94202 7. typical operating conditions ........... ........... .......... ............................ .................. 32 8. cell fail detectio n .............. ........................... ................... ............... .............. ...... 33 9. open-wire detection ......... .............................................. ............... .............. ...... 34 10. current and voltage monitoring .............. ................................ ............................ 37 10.1 current monitor ........................................... ............................................................... ............. 37 10.2 current sense ............................................. ............................................................... ............. 37 10.3 overcurrent an d short-circuit detection ................... .............................................................. 40 10.4 overcurrent and short-circuit response (discharge) ........ .................................................... 40 10.5 overcurrent response (ch arge) ............................. ............................................................... 41 10.6 microcontroller overcurrent fet control protection ........ ....................................................... 42 10.7 voltage, temperature, an d current scan .................... ........................................................... 43 10.8 cell voltage monitoring ................................... ............................................................... ......... 44 10.8.1 uvlo and ovlo ........................................... ............................................................... ...... 44 10.8.2 uv, ov, and sleep ....................................... ............................................................... ........ 44 10.9 overvoltage detection/response ............................ ............................................................... 46 10.10 undervoltage detection/ response .......................... ............................................................... 48 10.11 temperature monitoring/response .......................... ............................................................... 49 10.11.1 over-temperature ....................................... ............................................................... ......... 50 10.11.2 under-temperature ...................................... ............................................................... ........ 50 10.12 microcontroller read of voltages ......................... ............................................................... .... 52 10.13 voltage conversions ...................................... ............................................................... .......... 53 10.13.1 cell voltages .......................................... ............................................................... .............. 53 10.13.2 pack current ........................................... ............................................................... ............. 53 10.13.3 temperature ............................................ ............................................................... ............. 53 10.13.4 14-bit register ........................................ ............................................................... ............. 53 11. microcontroller fet control ................................ ............. ............... .............. ...... 54 12. cell balance .... .............................. ............................ ................................. ......... 55 12.1 c control of cell balance fets ........................... ............................................................... .. 57 12.2 cell balance fet drive ................................................................................................... ....... 57 13. watchdog timer .............. ........................................................................... ......... 59 14. power fet drive ............................. ............... ............... ............................ ......... 60 15. general i/os .... ............... ........................................................................... ......... 61 16. higher voltage microcontrollers ........... ............................................. .................. 62 17. packs with fewer than eight c ells .......................... ............... ............................ 63
fn8889 rev.2.00 page 10 of 89 mar 8, 2017 isl94202 18. pc board layout ............ ................. ............... ............... ............................ ......... 64 18.1 qfn package ............................................... ............................................................... ........... 65 18.2 circuit diagrams .......................................... ............................................................... ............ 65 19. eeprom ......................................... ............ .............................................. ......... 66 20. serial interface .............................. ............................ ................................. ......... 67 20.1 serial interface conventions .............................. ............................................................... ...... 67 20.2 clock and data ............................................ ............................................................... ............ 67 20.3 start condition ........................................... ............................................................... .............. 67 20.4 stop condition ............................................ ............................................................... ............. 67 20.5 acknowledge ............................................... ............................................................... ............ 68 20.6 write operations .......................................... ............................................................... ............ 69 20.6.1 byte write .............................................. ............................................................... .............. 69 20.6.2 page write .............................................. ............................................................... ............. 69 20.7 read operations ........................................... ............................................................... ........... 70 20.7.1 current address read .................................... ............................................................... ..... 70 20.7.2 random read ............................................. ............................................................... ......... 70 20.7.3 sequential read ......................................... ............................................................... ......... 71 20.7.4 eeprom access ........................................... ............................................................... ...... 72 20.7.5 eeprom read ............................................. ............................................................... ....... 72 20.7.6 eeprom write ............................................ ............................................................... ........ 72 20.8 synchronizing microcontroller operations with internal scan ................................................ 72 21. register protection ....... ............................................................................. ......... 73 22. registers: summary (eeprom) ................ ................ ............... ................ ......... 74 23. registers: summary (ram) .. ...................... ............................ ............................ 75 24. registers: detailed (eeprom) .......... ..................... ............................................ 76 25. registers: detailed (ram) .. ................................ ............. ............... .............. ...... 82 26. revision history ............ ................ ............... .............................................. ......... 87 27. package outline drawing .... ................................ ................. .............................. 88
isl94202 3. specifications fn8889 rev.2.00 page 11 of 89 mar 8, 2017 3. specifications 3.1 absolute maximum ratings (note 1) caution: do not operate at or near the maximum ratings listed f or extended periods of time. exposure to such conditions may ad versely impact product reliability and re sult in failures not covered b y warranty. parameter minimum maximum (note 1) unit power supply voltage, vdd vss - 0.5 vss+ 45.0 v cell voltage (vc, vbatt) vcn -0.5 vbatt + 0.5 v vcn - vss (n = 8) -0.5 45.0 v vcn - vss (n = 6, 7) -0.5 36.0 v vcn - vss (n = 4, 5) -0.5 27.0 v vcn - vss (n = 2, 3) -0.5 17.0 v vcn - vss (n = 1) -0.5 7.0 v vcn - vss (n = 0) -0.5 3.0 v vcn - vc(n-1) (n = 2 to 12) -3.0 7.0 v vc1 - vc0 -0.5 7.0 v cell balance pin voltages (vcb) vcbn - vc(n-1), n = 1 to 5 -0.5 7.0 v vcn - vcbn, n = 6 to 8 -0.5 7.0 v terminal voltage addr, xt1, xt2, fetsoff, psd, int -0.5 vrgo +0.5 v scl, sdai, sdao, eoc , sd -0.5 5.5 v cfet, pcfet, c1, c2, c3 vdd - 0.5 vdd + 15.5 (60v max) v dfet, chmon, ldmon -0.5 vdd + 15.0 (60v max) v terminal current rgo 25 ma current-sense voltage vbatt, cs1, cs2 -0.5 vdd +1.0 v vbatt - cs1, vbatt - cs2 -0.5 +0.5 v cs1 - cs2 -0.5 +0.5 v esd rating value unit human body model (tested per js-001-2014) 1.5 kv charged device model (tested per js-002-2014) 1 kv latch-up (tested per jesd78e; class 2, level a) 100 ma note: 1. devices are characterized, but not production tested, at abso lute maximum voltages.
isl94202 3. specifications fn8889 rev.2.00 page 12 of 89 mar 8, 2017 3.2 thermal information 3.3 recommended ope rating conditions thermal resistance (typical) ? ja (c/w) ? jc (c/w) 48 ld qfn package ( notes 2 , 3 )2 8 0 . 7 5 notes: 2. ? ja is measured in free air with the component mounted on a high-e ffective thermal conductivity test board with direct attach features. see tech brief tb379 . 3. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. parameter minimum maximum unit continuous package power dissipation 400 mw maximum junction temperature +125 c storage temperature range -55 +125 c pb-free reflow profile see tb493 parameter minimum maximum unit temperature range -40 +85 c operating voltage vdd 4v 36 v vcn-vc(n-1) specified range 2.0 4.3 v vcn-vc(n-1) extended range 1.0 4.4 v vcn-vc(n-1) maximum range (any cell) 0.5 4.8 v
isl94202 3. specifications fn8889 rev.2.00 page 13 of 89 mar 8, 2017 3.4 electrical specification v dd = 26.4v, t a = -40c to +85c, unle ss otherwise specified. boldface specificati on limits apply across operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 4 ) typ max ( note 4 ) unit power-up condition C threshold rising (device becomes operational) v porr1 v dd minimum voltage at which device operation begins (cfet turns on; chmon = v dd ) 6.0 v v porr2 chmon minimum voltage at which device operation begins (cfet turns on; v dd > 6.0v) v dd v power-down condition C threshold falling v porf v dd minimum voltage device remains operational (rgo turns off) 3.0 v 2.5v regulated voltage v rgo i rgo = 3ma 2.4 2.5 2.6 v 1.8v reference voltage v ref 1.79 1.8 1.81 v vbatt input current - v batt i vbatt input current; normal/idle/doze modes v dd = 33.6v 38 45 a input current; sleep/power-down modes v dd = 33.6v 1 a v dd supply current i vdd1 device active (normal mode) (no error conditions) cfet, pcfet, dfet = off; v dd = 33.6v 310 370 a i vdd2 device active (idle mode) (no error conditions) idle = 1 cfet, pcfet, dfet = off; v dd = 33.6v 215 275 a i vdd3 device active (doze mode) (no error conditions) doze = 1 cfet, pcfet, dfet = off; v dd = 33.6v 210 265 a i vdd4 fet drive current (i vdd increase when fets are on - normal/idle/doze modes); v dd = 33.6v 215 a i vdd5 device active (sleep mode); sleep = 1; v dd = 33.6v 0c to +60c 13 30 a -40c to +85c 50 a i vdd6 power-down pdwn = 1; v dd = 33.6v 1 a input bias current ics1 v dd = v batt = vcs1 = vcs2 = 33.6v (normal, idle, doze) 10 15 a v dd = v batt = vcs1 = vcs2 = 33.6v (sleep, power-down) 0c to +60c 1 a -40c to +85c 3 a ics2 v dd = v batt = vcs1 = vcs2 = 33.6v (normal, idle, doze) 10 15 a v dd = v batt = vcs1 = vcs2 = 33.6v (sleep, power-down) 0c to +60c 1 a -40c to +85c 3 a vcn input current i vcn cell input leakage current ao2:ao0 = 0000h (normal/idle/doze; not sampling cells) -1 1 a cbn input current i cbn cell balance pin leakage current (no balance active) -1 1 a
isl94202 3. specifications fn8889 rev.2.00 page 14 of 89 mar 8, 2017 temperature monitor specifications external temperature accuracy v xt1 external temperature monitoring error. adc voltage error when monitoring xt1 input. tgain = 0; (xtn = 0.2v to 0.737v) -25 15 mv internal temperature monitor output (see temperature monitoring/response on page 49 ) t int25 [itb:it0] 10 *1.8/4095/gain gain = 2 (tgain bit = 0) temperature = +25c 0.276 v v intmon change in [itb:it0] 10 *1.8/4095/gain gain = 2 (tgain bit = 0) temperature = -40c to +85c 1.0 mv/c cell voltage monitor specifications cell monitor voltage accuracy (relative) v adcr relative cell measurement error (maximum absolute cell measurement error - minimum absolute cell measurement error) vcn - vc(n-1) = 2.4v to 4.2v; 0c to +60c 310mv vcn - vc(n-1) = 0.1v to 4.7v; 0c to +60c 15 mv vcn - vc(n-1) = 0.1v to 4.7v; -40c to +85c 30 mv cell monitor voltage accuracy (absolute) v adc absolute cell measurement error (cell measurement error compared with voltage at the cell) vcn - vc(n-1) = 2.4v to 4.2v; 0c to +60c -15 15 mv vcn - vc(n-1) = 0.1v to 4.7v; 0c to +60c -20 20 mv vcn - vc(n-1) = 0.1v to 4.7v; -40c to +85c -30 30 mv v batt voltage accuracy v batt v batt - [vbb:vb0] 10 *32*1.8/4095; 0c to +60c -200 200 mv -40c to +85c -270 270 mv current-sense amplifier specifications charge current threshold vccth vcs1-vcs2, ching indicates charge current vcs1 = 26.4v -100 v discharge current threshold vdcth vcs1-vcs2, dching indicates discharge current; vcs1 = 26.4v 100 v v dd = 26.4v, t a = -40c to +85c, unle ss otherwise specified. boldface specificati on limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 4 ) typ max ( note 4 ) unit
isl94202 3. specifications fn8889 rev.2.00 page 15 of 89 mar 8, 2017 current-sense accuracy via1 v ia1 = ([isnsb:isns0] 10 *1.8/4095)/5; ching bit set; gain = 5 vcs1 = 26.4v, vcs2 - vcs1 = + 100mv 97 102 107 mv via2 v ia2 = ([isnsb:isns0] 10 *1.8/4095)/5; dching bit set; gain = 5 vcs1 = 26.4v, vcs2 - vcs1 = - 100mv -107 -102 -97 mv via3 v ia3 = ([isnsb:isns0] 10 *1.8/4095)/50; ching bit set; gain = 50 vcs1 = 26.4v, vcs2 - vcs1 = + 10mv 8.0 10.0 12.0 mv via4 v ia4 = ([isnsb:isns0] 10 *1.8/4095)/50; dching bit set; gain = 50 vcs1 = 26.4v, vcs2 - vcs1 = - 10mv -12.0 -10.0 -8.0 mv via5 v ia3 = ([isnsb:isns0] 10 *1.8/4095)/500; ching bit set; gain = 500 vcs1 = 26.4v, vcs2 - vcs1 = + 1mv 0c to +60c 0.5 1.0 1.5 mv -40c to +85c 0.4 1.6 mv via6 v ia4 = ([isnsb:isns0] 10 *1.8/4095)/500; dching bit set; gain = 500 vcs1 = 26.4v, vcs2 - vcs1 = - 1mv 0c to +60c -1.5 -1.0 -0.5 mv -40c to +85c -1.6 -0.4 mv overcurrent/short-circuit protection specifications discharge overcurrent detection threshold v ocd v ocd = 4mv [ocd2:0] = 0,0,0 2.6 4.0 5.4 mv v ocd = 8mv [ocd2:0] = 0,0,1 6.4 8.0 9.6 mv v ocd = 16mv [ocd2:0] = 0,1,0 12.8 16.0 19.2 mv v ocd = 24mv [ocd2:0] = 0,1,1 20 25 30 mv v ocd = 32mv [ocd2:0] = 1,0,0 (default) 26.4 33.0 39.6 mv v ocd = 48mv [ocd2:0] = 1,0,1 42.5 50.0 57.5 mv v ocd = 64mv [ocd2:0] = 1,1,0 60.3 67.0 73.7 mv v ocd = 96mv [ocd2:0] = 1,1,1 90 100 110 mv discharge overcurrent detection time t ocdt [ocdta:ocdt0] = 0a0h (160ms) (default) range: 0ms to 1023ms 1ms/step 0s to 1023s; 1s/step 160 ms short-circuit detection threshold v scd v scd = 16mv [scd2:0] = 0,0,0 10.4 16.0 21.6 mv v scd = 24mv [scd2:0] = 0,0,1 18 24 30 mv v scd = 32mv [scd2:0] = 0,1,0 26 33 40 mv v scd = 48mv [scd2:0] = 0,1,1 42 49 56 mv v scd = 64mv [scd2:0] = 1,0,0 60 67 74 mv v scd = 96mv [scd2:0] = 1,0,1 (default) 90 100 110 mv v scd = 128mv [scd2:0] = 1,1,0 127 134 141 mv v scd = 256mv [scd2:0] = 1,1,1 249 262 275 mv short-circuit current detection time t sct [scta:sct0] = 0c8h (200s) (default) range: 0s to 1023s; 1s/step 0ms to 1023ms 1ms/step 200 s v dd = 26.4v, t a = -40c to +85c, unle ss otherwise specified. boldface specificati on limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 4 ) typ max ( note 4 ) unit
isl94202 3. specifications fn8889 rev.2.00 page 16 of 89 mar 8, 2017 charge overcurrent detection threshold v occ v occ = 1mv [occ2:0] = 0,0,0 0.2 1.0 2.1 mv v occ = 2mv [occ2:0] = 0,0,1 0.7 2.0 3.3 mv v occ = 4mv [occ2:0] = 0,1,0 2.8 4.0 5.2 mv v occ = 6mv [occ2:0] = 0,1,1 4.5 6.0 7.5 mv v occ = 8mv [occ2:0] = 1,0,0 (default) 6.6 8.0 9.8 mv v occ = 12mv [occ2:0] = 1,0,1 9.6 12.0 14.4 mv v occ = 16mv [occ2:0] = 1,1,0 14.5 17.0 19.6 mv v occ = 24mv [occ2:0] = 1,1,1 22.5 25.0 27.5 mv overcurrent charge detection time t occt [occta:occt0] = 0a0h (160ms) (default) range: 0ms to 1023ms 1ms/step 0s to 1023s; 1s per step 160 ms charge monitor input threshold (falling edge) v chmon ccmon bit = 1; cmon_en bit = 1 8.2 8.9 9.8 v load monitor input threshold (rising edge) v ldmon clmon bit = 1; lmon_en bit = 1 0.45 0.60 0.75 v load monitor output current i ldmon clmon bit = 1; lmon_en bit = 1 62 a voltage protection specifications overvoltage lockout threshold (rising edge - any cell) [vcn-vc(n-1)] v ovlo [ovlob:ovlo0] = 0e80h (4.35v) (default) range: 12-bit value (0v to 4.8v) 4.35 v overvoltage lockout recovery threshold - all cells v ovlor falling edge v ovr v undervoltage lockout threshold (falling edge - any cell) [vcn-vc(n-1)] v uvlo [uvlob:uvlo0] = 0600h (1.8v) (default) range: 12-bit value (0v to 4.8v) 1.8 v undervoltage lockout recovery threshold - all cells v uvlor rising edge v uvr v overvoltage lockout detection time t ovlo normal operating mode 5 consecutive samples over the limit (minimum = 160ms, maximum = 192ms) 176 ms undervoltage lockout detection time t uvlo normal operating mode 5 consecutive samples under the limit (minimum = 160ms, maximum = 192ms) 176 ms overvoltage threshold (rising edge - any cell) [vcn-vc(n-1)] v ov [ovlb:ovl0] = 0e2ah (4.25v) (default) range: 12-bit value (0v to 4.8v) 4.25 v overvoltage recovery voltage (falling edge - all cells) [vcn-vc(n-1)] v ovr [ovrb:ovr0] = 0dd5h (4.15v) (default) range: 12-bit value (0v to 4.8v) 4.15 v overvoltage detection/release time t ovt [ovta:ovt0] = 201h (1s) (default) range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1s undervoltage threshold (falling edge - any cell) [vcn-vc(n-1)] v uv [uvlb:uvl0] = 0900h (2.7v) (default) range: 12-bit value (0v to 4.8v) 2.7 v undervoltage recovery voltage (rising edge - all cells) [vcn-vc(n-1)] v uvr [uvrb:uvr0] = 0a00h (3.0v) (default) range: 12-bit value (0v to 4.8v) 3.0 v undervoltage detection time t uvt [uvta:uvt0] = 201h (1s) (default) range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1s v dd = 26.4v, t a = -40c to +85c, unle ss otherwise specified. boldface specificati on limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 4 ) typ max ( note 4 ) unit
isl94202 3. specifications fn8889 rev.2.00 page 17 of 89 mar 8, 2017 undervoltage release time t uvtr [uvta:uvt0] = 201h (1s) + 3s (default) range: (0ms to 1023ms) + 3s; 1ms/step (0s to 1023s) + 3s; 1s/step 3s sleep voltage threshold (falling edge - any cell) [vcn-vc(n-1)] v sll [sllb:sll0] = 06aah (2.0v) (default) range: 12-bit value (0v to 4.8v) 2.0 v sleep detection time t slt [slta:slt0] = 201h (1s) (default) range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1s low voltage charge threshold (falling edge - any cell) [vcn-vc(n-1)] v lvch [lvchb:lvch0] = 07aah (2.3v) (default) range: 12-bit value (0v to 4.8v) precharge if any cell is below this voltage 2.3 v low voltage charge threshold hysteresis v lvchh 117 mv end-of-charge threshold (rising edge - any cell) [vcn-vc(n-1)] v eoc [eocsb:eocs0] = 0e00h (4.2v) (default) range: 12-bit value (0v to 4.8v) 4.2 v end-of-charge threshold hysteresis v eoch 117 mv sleep mode timer t smt [mod7:mod0] = 0dh (off) (default) range: 0s to 255 minutes 90 min watchdog timer t wdt [wdt4:wdt0] = 1fh (31s) (default) range: 0s to 31s 31 s temperature protection specifications internal temperature shutdown threshold t itsd [iotsb:iots0] = 02d8h 115 c internal temperature recovery t itrcv [iotrb:iotr0] = 027dh 95 c external temperature output voltage v tempo voltage output at tempo pin (during temperature scan); i tempo = 1ma 2.30 2.45 2.60 v external temperature limit threshold (hot) - xt1 or xt2 charge, discharge, cell balance (see figure 3.1 ) t xth xtn hot threshold. voltage at v tempi , xt1 or xt2 = 04b6h tgain = 0 ~+55c; thermistor = 3.535k detected by cot, dot, cbot bits = 1 0.265 v external temperature recovery threshold (hot) - xt1 or xt2 charge, discharge, cell balance (see figure 3.1 ) t xthr xtn hot recovery voltage at v tempi xt1 or xt2 = 053eh tgain = 0 (~+50c; thermistor = 4.161k) detected by cot, dot, cbot bits = 0 0.295 v external temperature limit threshold (cold) - xt1 or xt2 charge, discharge, cell balance (see figure 3.1 ) t xtc xtn cold threshold. voltage at v tempi xt1 or xt2 = 0bf2h tgain = 0 (~ -10c; thermistor = 42.5k) detected by cut, dut, cbut bits 0.672 v external temperature recovery threshold (cold) - xt1 or xt2 charge, discharge, cell balance (see figure 3.1 ) t xtch xtn cold recovery voltage at v tempi . xt1 or xt2 = 0a93h tgain = 0 (~5c; thermistor = 22.02k) detected by cut, dut, cbut bits 0.595 v cell balance specifications cell balance fet gate drive current vc1 to vc5 (current out of pin) 15 25 35 a vc6 to vc8 (current into pin) 15 25 35 a v dd = 26.4v, t a = -40c to +85c, unle ss otherwise specified. boldface specificati on limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 4 ) typ max ( note 4 ) unit
isl94202 3. specifications fn8889 rev.2.00 page 18 of 89 mar 8, 2017 cell balance maximum voltage threshold (rising edge - any cell) [vcmax] v cbmx [cbvub:cbvu0] = 0e00h (4.2v) (default) range: 12-bit value (0v to 4.8v) 4.2 v cell balance maximum threshold hysteresis v cbmxh 117 mv cell balance minimum voltage threshold (falling edge - any cell) [vcmin] v cbmn [cbvlb:cbvl0] = 0a00h (3.0v) (default) range: 12-bit value (0v to 4.8v) 3.0 v cell balance minimum threshold hysteresis v cbmnh 117 mv cell balance maximum voltage delta threshold (rising edge - any cell) [vcn-vc(n-1)] v cbdu [cbdub:cbd0] = 06aah (2.0v) (default) range: 12-bit value (0v to 4.8v) 2.0 v cell balance maximum voltage delta threshold hysteresis v cbduh 117 mv wake-up specifications device chmon pin voltage threshold (wake on charge) (rising edge) v wkup1 chmon pin rising edge device wakes up and sets sleep flag low 7.0 8.0 9.0 v device ldmon pin voltage threshold (wake on load) (falling edge) v wkup2 ldmon pin falling edge device wakes up and sets sleep flag low 0.15 0.40 0.70 v open-wire specifications open-wire current i ow 1.0 ma open-wire detection threshold v ow1 vcn-vc(n-1); vcn is open. (n = 2, 3, 4, 5, 6, 7, 8). open-wire detection active on the vcn input. -0.3 v v ow2 vc1-vc0; vc1 is open. open-wire detection active on the vc1 input. 0.4 v v ow3 vc0-vss; vc0 is open. open-wire detection active on the vc0 input. 1.25 v fet control specifications dfet gate voltage v dfet1 (on) 100a load; v dd = 36v 47 52 57 v v dfet2 (on) 100a load; v dd = 6v 8 9 10 v v dfet3 (off) 0v cfet gate voltage (on) v cfet1 (on) 100a load; v dd = 36v 47 52 57 v v cfet2 (on) 100a load; v dd = 6v 8 9 10 v v cfet3 (off) v dd v pcfet gate voltage (on) v pfet1 (on) 100a load; v dd = 36v 47 52 57 v v pfet2 (on) 100a load; v dd = 6v 8 9 10 v v pfet3 (off) v dd v fet turn-off current (dfet) i df(off) 14 15 16 ma fet turn-off current (cfet) i cf(off) 9 13 17 ma fet turn-off current (pcfet) i pf(off) 9 13 17 ma fetsoff rising edge threshold v fo(ih) fetsoff rising edge threshold. turn off fets 1.8 v fetsoff falling edge threshold v fo(il) fetsoff falling edge threshold. turn on fets 1.2 v serial interface characteristics ( note 5 ) input buffer low voltage (scl, sda) v il voltage relative to v ss of the device -0.3 v rgo x 0.3 v input buffer high voltage (scl, sdai, sdao) v ih voltage relative to v ss of the device v rgo x 0.7 v rgo +0.1 v v dd = 26.4v, t a = -40c to +85c, unle ss otherwise specified. boldface specificati on limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 4 ) typ max ( note 4 ) unit
isl94202 3. specifications fn8889 rev.2.00 page 19 of 89 mar 8, 2017 output buffer low voltage (sda) v ol i ol = 1ma 0.4 v sda and scl input buffer hysteresis i 2 chyst sleep bit = 0 0.05 x v rgo v scl clock frequency f scl 400 khz pulse width suppression time at sda and scl inputs t in any pulse narrower than the maximum spec is suppressed. 50 ns scl falling edge to sda output data valid t aa from scl falling crossing v ih (minimum), until sda exits the v il (maximum) to v ih (minimum) window 0.9 s time the bus must be free before start of new transmission t buf sda crossing v ih (minimum) during a stop condition to sda crossing v ih (minimum) during the following start condition 1.3 s clock low time t low measured at the v il (maximum) crossing 1.3 s clock high time t high measured at the v ih (minimum) crossing 0.6 s start condition set-up time t su:sta scl rising edge to sda falling edge, both crossing the v ih (minimum) level 0.6 s start condition hold time t hd:sta from sda falling edge crossing v il (maximum) to scl falling edge crossing v ih (minimum) 0.6 s input data set-up time t su:dat from sda exiting the v il (maximum) to v ih (minimum) window to scl rising edge crossing v il (minimum) 100 ns input data hold time t hd:dat from scl falling edge crossing v ih (minimum) to sda entering the v il (maximum) to v ih (minimum) window 00.9 s stop condition set-up time t su:sto from scl rising edge crossing v ih (minimum) to sda rising edge crossing v il (maximum) 0.6 s stop condition hold time t hd:sto from sda rising edge to scl falling edge. both crossing v ih (minimum) 0.6 s data output hold time t dh from scl falling edge crossing v il (maximum) until sda enters the v il (maximum) to v ih (minimum) window 0 ns sda and scl rise time t r from v il (maximum) to v ih (minimum) 300 ns sda and scl fall time t f from v ih (minimum) to v il (maximum) 300 ns sda and scl bus pull-up resistor off-chip r out maximum is determined by t r and t f for c b = 400pf, maximum is 2k ~ 2.5k for c b = 40pf, maximum is 15k ? ~ 20k 1 k input leakage (scl, sda) i li - 10 10 a eeprom write cycle time t wr +25c 30 ms notes: 4. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. device min and/or max values are based on temperature li mits established by character ization and are not production tested. 5. compliance to datasheet limits is assured by one or more methods: production test, charac terization, and/or design. v dd = 26.4v, t a = -40c to +85c, unle ss otherwise specified. boldface specificati on limits apply across operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 4 ) typ max ( note 4 ) unit
isl94202 3. specifications fn8889 rev.2.00 page 20 of 89 mar 8, 2017 3.5 symbol table 3.6 timing diagrams 3.6.1 external temperature configuration waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs thermistors: 10k, murata xh103f 10k 10k xt2 pin xt1 pin tempo pin 22k 22k figure 3.1 external tem perature configuration digital temperature voltage reading = xtn * 2 (tgain bit = 0) xtn * 1 (tgain bit = 1)
isl94202 3. specifications fn8889 rev.2.00 page 21 of 89 mar 8, 2017 3.6.2 wake-up timing 3.6.3 power-up timing ldmon pin in_sleep bit v wkup2 <1s v wkup1 <1s chmon pin in_sleep bit figure 3.2 wake-up timing (from sleep) can stay in sleep mode dfet/cfet ~140ms ~50ms enters sleep mode if ldmon or chmon is ?active? when entering sleep mode, the ic wakes up after a short delay. can stay in sleep mode can stay in sleep mode can stay in sleep mode chmon pin vwkup1 figure 3.3 power-up timing (from power-up/shutdown) dfet/cfet ~3s ldmon check 256ms turn on fets if no pack faults i 2 c communication ~4ms rgo
isl94202 3. specifications fn8889 rev.2.00 page 22 of 89 mar 8, 2017 3.6.4 change in fet control bit 0 dfet/cfet turn on sda scl bit 0 data bit 1 bit 1 bit 3 bit 2 ack ack 10% 90% t fton 10% 90% t ftoff figure 3.4 i 2 c fet control timing ~1s ~1s (~500s if both fets off) dfet/cfet ~1s figure 3.5 fetsoff fet control timing ~1s fetsoff pin v fo(on) v fo(off) fet ~500s turn on charge pump
isl94202 3. specifications fn8889 rev.2.00 page 23 of 89 mar 8, 2017 3.6.5 automatic temperature scan 3.6.6 serial interface timing diagrams tempo pin delay time = 20s 128ms monitor 2.5v cbot, dot, cot bits external over-temperature delay time = 20s fet shutdown or monitor temperature during this time period threshold temperature figure 3.6 automatic temperature scan over-temp under-temp xtn xt1 xt2 xt1 xt2 1024ms 2048ms see figure 3.1 for test circuit off (if enabled) cell balance turn time = 120s t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl t f t low t buf t r t dh t aa sda (input timing) sda (output timing) figure 3.7 serial interface bus timing
isl94202 3. specifications fn8889 rev.2.00 page 24 of 89 mar 8, 2017 3.6.7 discharge overcurrent/short-circuit monitor 3.6.8 charge overcurrent monitor (assumes no_o ccr bit is 0) v sc v ocd t scd t ocd t scd doc bit dsc bit sd v dsense c register 1 read c register 1 read output 2.5v 1 1 0 0 dfet output isl94202 turns on dfet c is optional ldmon detects load release ldmon detects resets doc, scd bit, turns on fet resets doc, scd bit, figure 3.8 discharge/short-circuit monitor (cfet bit = 0) v dd +15v v ldmon load releases during this time ldmon pin detects 2 ldmon puls es above threshold 3s 256ms load release turns on fet v occ t occ coc bit sd v csense register 1 read output 2.5v 1 0 cfet output isl94202 turns on cfet v dd +15v chmon detects charger release resets doc, scd bit, turns on fet (cfet bit = 0) figure 3.9 charge overcurrent monitor v chmon charger releases chmon pin detects 2 chmon puls es below threshold
isl94202 4. functional description fn8889 rev.2.00 page 25 of 89 mar 8, 2017 4. functional description this ic is intended to be a stand-alone bat tery pack monitor, s o it provides monitor and protection functions without requirin g an external microcontroller. the part operates power control f ets on the high side with a bu ilt-in charge pump for driving n-channel fets. the current-sense function is also on the high side. to extend battery life, power i s minimized in all areas with pa rts of the circuit powered down a majority of the time. the rg o output stays on so that any conn ected microcontroller can remai n on most of the time. the isl94202 includes: ? input level shifter to enable monitoring of battery stack volt ages ? 14-bit adc converter, with voltage readings trimmed and saved as 1 2-bit results ? 1.8v voltage refer ence (0.8% accurate) ? 2.5v regulator, with the voltage maintained during sleep ? automatic scan of the cell volt ages; overvoltage, undervoltage , and sleep voltage monitoring ? selectable overcurrent detection settings ? eight discharge overcurrent thresholds ? eight charge overcurrent thresholds ? eight short-circuit thresholds ? 12-bit programmable discharge overcurrent delay time ? 12-bit programmable charge overcurrent delay time ? 12-bit programmable s hort-circuit delay time ? current-sense monitor with gain that provides the ability to r ead the current-sense voltage ? second external temperature sensor for use in monitoring the p ack or power f et temperatures ? eeprom for storing operating parameters and a user area for ge neral purpose pack information
isl94202 5. battery connections fn8889 rev.2.00 page 26 of 89 mar 8, 2017 5. battery connections 5.1 power path figure 5.1 shows the main power path connections for a single charge/disc harge path. these figures show schottky diodes on the vdd pin. these are to maintain the voltage on the vdd pin during high current conditions or when the charge f et is off. these are not needed if v dd can be maintained within 0.5v of v batt . the chmon pin connects to the p ack pin that receives the charge and the ldmon pin connects to the pack pin that drives the load. for the single path application, these pins can tie t ogether. vbatt cs2 pack+ cfet ldmon n-channel fets chmon pcfet 1k 47nf bat+ 1k 47nf figure 5.1 single path fet drive/power supply detail chg+ dischg+ 100 470nf cs1 vc8 vc7 vdd dfet
isl94202 5. battery connections fn8889 rev.2.00 page 27 of 89 mar 8, 2017 5.2 pack configuration a register in eeprom (cells) identifies the number of cells tha t are supposed to be present, so the isl94202 only scans these cells. this register is also used for the cell balance op eration. the register contents are a 1:1 representation of the cells connected to the pack. for exampl e, in a 6-cell pack, the value in cells is 11100111 (cfh), which indicates that cells 1, 2, 3, 6, 7, and 8 ar e connected. also see figure 5.2 . 5.3 battery cell connections suggested connections for pack configurations varying from thre e cells to eight cel ls are shown in figure 5.2 . note: multiple cells can be connected in parallel 6 cells 3 cells 4 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss 8 cells cb7 cb6 cb5 cb4 cb3 cb2 cb1 figure 5.2 battery connection options vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 5 cells 7 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0
isl94202 6. operating modes fn8889 rev.2.00 page 28 of 89 mar 8, 2017 6. operating modes 6.1 power-up operation when the isl94202 first connects to the battery pack, it is unk nown which pins conn ect first or in what order. when the vdd and vss pins conn ect, the device enters the power-down stat e. it remains in this state un til a charger is connected. the device will also power up if the chmon pin is connected to the vdd pin through an outside resistor to simplify the pcb manufacture. it is possible that the pack powers up automat ically when the battery stack is connected due to momentary conduction through th e power fet g-s and g-d capacito rs. once the charger connects (or chmon connects), the internal pow er supply turns on. this pow ers up all internal supplies and starts the state machine. if some cells are not connected, the state machine recognizes this, either through the open-wire test (see typical operating conditions on page 32 ) or because the monit ored cell volt age reads zero when the ce lls register indicates tha t there should be a vo ltage at that pin. if the cell voltages do not read correctly, then the isl94202 remains in the por loop until conditions are valid for power-up . (it is for this reason that the factory default for the devic e is three cells. when manufacturing the application board, cells 1, 2, and 8 must be connected to power up. if other cells are connected it is ok, but for the o ther cells to be monitored, th e cells register need s to be changed.) if the inputs all read good dur ing this sequence, then the st ate machine enters t he normal monitor st ate. in the normal state, if all cell voltages read good and there are no overcu rrent or temperature issues and th ere is no load, the fets turn on. to determine if there is a load, the device does a load che ck. this operation waits for about three seconds and then must see no load for two successive loa d monitor cycles (256ms apart). during the por operation, the ram registers are all reset to de fault conditions from values saved in the eeprom. when the cell voltages drop, the isl94202 remains on if the v dd voltage remains above 1v and the vrgo voltage is above 2.25v. this is to maintain operation of the device in the event of a short drop in cell voltage due to a pack short- circuit condition. in the event of a longer battery stack volta ge drop, the device will retur n to a power-down condition if v dd drops below a por threshold of about 3.5v when v rgo is below 2.25v (see figures 6.14 and 6.15 ). power on reset fets off, no current scan. power-down state charger connect scan only voltages, temp, load all voltages ok temp ok ? do a voltage scan. ? only look at cells that are specified in the cell reg. ? if all cell voltages and temps are ok, do a load test. ? if there are any errors, keep scanning voltages, temperatures, and load at normal scan rates. normal operating mode figure 6.14 power-on reset state machine no load v rgo < 1.2v (any cell < v uvlo for 160ms and or or pdwn bit set battery stack connect and v dd > v por uvlopd = 1)
isl94202 6. operating modes fn8889 rev.2.00 page 29 of 89 mar 8, 2017 6.2 wake-up circuit when in sleep mode, the wake-up circuit det ects that the output pin is pulled low (as might b e the case when a load is attached to the pack a nd the fets are off) or pulled high (as m ight be the case when the charg er is connected and the fets are off). the wake-up circuit does not draw significant continuous curren t from the battery. 6v vdd last cell connected por scan rgo por (reset 2.25v uv uvr dfet figure 6.15 power-up/power-down low voltage waveforms por ~3.5v while rgo is above 2.25v, v dd dropping below por does not cause a power-down powered state chmon registers) ldmon 3s
isl94202 6. operating modes fn8889 rev.2.00 page 30 of 89 mar 8, 2017 6.3 low power states in order to minimize power consumption, mos t circuits are kept off when not being used an d items are sampled when possible. there are five power sta tes in the device (see figure 6.16 ). 6.3.1 normal mode this is the normal monitoring/scan mode. in this mode, the devi ce monitors the current continuously and scans the voltages every 32ms. if balancing is called for, then the devic e activates external balanci ng components. all necessary circuits are on and unnece ssary circuit s are off. during the scan, the isl94202 dra ws more current as it activate s the input level shifter, t he adc, and data processing. between scans, circuits turn off to minimize power consumption. 6.3.2 idle mode if there is no current flowing fo r 0 to 15 minutes (set in the mod register), then the device enters the idle mode. in this mode, voltage scanning slows to every 256ms per scan. the fets and the ldo remain on. i n this mode, the device consumes less current, because t here is more time between scans . when the isl94202 detects any charge or discharge current, the device exits the idle mode a nd returns to the normal mode of operation. the device does not automatically enter the idle mode if the c scan bit is set to 1, because the microcontroller is in charge of performing the scan and controlling the operation. setting the idle bit to 1 forces the device to enter idle mod e, regardless of current flow. w hen a c sets the idle bit, the device remains in idle, regardless of the timer or the current. setting the mode control bits to 0 allows the device to control the mode. 6.3.3 doze mode while in idle mode, if there is n o current flowing for another 0 to 16 minutes (same value as the idle timer), the device enters the doze mode, where cell voltage sampling occurs every 512ms. the fets and the ld o remain on. in this mode, the device consumes less current than in idle mode, becau se there is more time between scans. when the isl94202 detects any charge or discharge current, the device exits doze mode and returns to the normal mode. the device does not automatically enter the idle mode if the c scan bit is set to 1, because the microcontroller is in charge of performing the scan and controlling the operation. setting the doze bit forces the d evice to enter the doze mode, regardless of the current flow. when a microcontroller sets the doze bit, the device re mains in doze mode regardless o f the timer or the current. setting the mode control bits to 0 allows the device to control the mode. note: setting the idle/doze timer to 0 immediately forces the d evice into the do ze mode when ther e is no current. 6.3.4 sleep mode the isl94202 enters the sleep mode when the voltage on the cell s drops below the sleep voltage threshold for a period of time, specified by the sleep delay timer . to prevent the dev ice from entering the sleep mode by a low voltage on the cells, the sleep voltage level ( sll) register can be set to 0 . the device can also enter the sl eep mode from the doze mode if there has been no detected c urrent for more than the duration of the sleep mode timer (set in the mod register). in this case, the device remains in doze mode until there has been no current for 0 to 240 minutes (with 16 minute steps). the external microcontroller for ces the isl94202 to enter sleep mode by writing to the sleep bit (register 88h). setting the sleep bit forces t he sleep mode, regardless of the current flow.
isl94202 6. operating modes fn8889 rev.2.00 page 31 of 89 mar 8, 2017 note: if both idle/do ze and sleep timers ar e set to 0, the de vice immediately goes to sl eep. to recover from this condition, apply current to the device or hold the ldmon pin low (or chmon pin high) and write non-zero values to the registers. while in the sleep mode , everything i s off except for the 2.5v regulator and the wake up circuits. the device can be waken by ldmon connection to a l oad or chmon connection to a ch arger. 6.3.5 power-down mode this mode occurs when the voltage on the pack is too low for pr oper operation. this occurs when: ?v dd is less than the por threshold and rgo < 2.25v. this condition occurs if cells discharge over a long peri od of ti me. ?v dd is less than 1v and rgo > 2.25v . this condition can occur duri ng a short-circuit with minimum capacity cells . the v dd drops out, but the rgo cap maintains the logic supply. ? any cell voltage is less than the uvlo threshold for more than about 160ms (and uvlopd = 1). ? commanded by an external c. recovering out of any low power state brings the isl94202 into the normal operating mode. 6.3.6 exceptions there is one exception to the normal sequence of mode managemen t. when the microcontroll er sets the cscan bit, the internal scan stops . this means that the device no longer l ooks for the conditions requi red for sleep. the external microcontroller needs to man age the modes of operation. any cell voltage drops below sleep threshold for sleep delay time or sleep bit is set {any cell voltage less than uvlo for 160ms and uvlopd = 1} or rgo < 1.2v or pdwn bit set to 1 power-down state normal operating state power consumption average first power up: voltage on vdd rises above the por threshold. already powered: a charger wake up signal. power consumption <1a 450a (2ma peaks) idle state no charge or discharge curr ent detected for 0 to 15 min from normal state or idle bit is set power consumption average 350a max (2ma peaks) doze state no charge or discharge current detected for 0 to 15 min from idle s tate or doze bit is set power consumption average 300a (2ma peaks) sleep state no charge or discharge current detected for 0 to 240 min from doze state or sleep bit is set power consumption average 15a wake up signal (either charger or load) figure 6.16 isl94202 power states when the device detects any charge or discharge current, operation moves from doze or idle states back to the normal operating state
isl94202 7. typical operating conditions fn8889 rev.2.00 page 32 of 89 mar 8, 2017 7. typical operating conditions table 7.2 shows some typical device operating parameters. table 7.2 typical operating conditions function typical unit adc resolution 14 bits adc results saved (and calibrated) 12 bits adc conversion time 10 s overcurrent/short-circuit scan time continuous voltage scan time (time per cell) includes settling time 125 s voltage protection scan rate (time between scans) normal mode; idle mode doze mode 32 256 512 ms internal over-temperature turn-on/turn-off delay time 128 ms external temperature autoscan on time; tempo = 2.5v 0.2 ms external temperature autoscan off time; tempo = 0v normal mode idle mode doze mode 128 1024 2048 ms wake-up delay from sleep. time to turn on power fets following load or charger connection. all pack conditions ok. 140 ms wake-up delay from shutdown or initial power-up. time to turn o n power fets following charger connection. all pack conditions ok. 3s e c default idle/doze mode delay times 10 min default sleep mode delay time 90 min
isl94202 8. cell fail detection fn8889 rev.2.00 page 33 of 89 mar 8, 2017 8. cell fail detection the cell fail (cellf) condition indicates that the difference b etween the highest voltage cel l and the lowest voltage cell exceeds a programmed threshold (a s specified in t he cbdu regist er). once detected, the cellf condition turns off the cell balance fets and the power fets, but only if the cfet bit = 0 . setting the cfet bit = 1 pr events the power fets from turning off during a cellf condition. the microcontroller is then responsible for the power fet control. an eeprom bit, cfpsd, when set to 1, enables the psd activati on when the isl94202 detects a cell fail condition. when cellf = 1 and cfpsd = 1, the pow er fets and cell balance fets t urn off, plus the psd out put goes active. the pack designer can use the psd pin out put to deactivate the pack by b lowing a fuse. the cellf function can be disabled by setting the cbdu value to fffh. in this case, the volta ge differential can never exceed the limit. however, dis abling the cell fail condition al so disables the open-wire detection (see open-wire detection on page 34 ).
isl94202 9. open-wire detection fn8889 rev.2.00 page 34 of 89 mar 8, 2017 9. open-wire detection the isl94202 device has a special , open-battery wire detection function that prevents the cells from being excessively charged or discharged by turning off the power fets if there is an open wire. additionally, the open-wi re detection function prevents the operation of cell balancing when there is an open wire. cel l balancing with an open wire should be avoided for two reasons . first, an open wire compromise s cell balancing. second, excessive voltage may appear on the isl94202 vcn input pins if the cell balance turns on the external balancing fet when there is an open wire. internal clamps an d input series resistors preven t damage as a result of short ter m exposure to higher input volta ges. the open-wire f eature uses built in circuits to force short pul ses of current into or out o f the input capacitors (see figure 9.17 ). when there is no open wire, the battery cell itself changes lit tle in response to th e open-wire test. the open-wire operat ion is disabled by setting a control bit (dowd) to 1. when enabled (dowd = 0), the isl94202 performs an open-wire test when the cellf condition exists and then once every 32 voltage scans as long as the cellf condition remains. a cellf conditi on is the first indication th at there might be an open wire. in operation, the open-wire circuit pulls (or pushes) 1ma of cu rrent sequentially on each vcn input for a period of time. the open-wire on-time is programmable by a value in the owt registe r. the pulse duration is programmable between 1s and 512ms. the default values for cur rent and time are 1ma current and 1ms duration. note that, in the absence of a battery cell, 1ma input current, along with an external capacitor of 4.7nf, c hanges the voltage of the input to the open-wire threshold of -1.4v (relative to the adjacent cell) within 30s. with the cel l present, the voltage will have a negligible change. each input has a compa rator that detects if the voltage on an i nput drops more than 1.4v below the voltage of the cell below. exceptions are vc1 and vc0. for vc1, the circuit looks to see i f the voltage drops below 1v. for vc0, the circuit looks to see if the voltage exceeds 1.4v. if a ny comparator trips, then the device sets an open error flag indicating an open-wire failure and disables cell balancing. see figure 9.18 on page 35 for sample timing. figure 9.17 open-wire detection note: the open-wire test is run only if the device detects the cellf condition and then once every 32 voltage scans while a cellf condition exists. each current source is turned on sequentially. internal 2.5v supply control logic cell n cell 4 cell 3 cell 2 cell 1 vc0 vc1 vc2 vc3 vc4 vcn
isl94202 9. open-wire detection fn8889 rev.2.00 page 35 of 89 mar 8, 2017 with the open-wire setting of 1 ma, input resistors of 1k creat e a voltage drop of 1v. this vol tage drop, combined with the body diode clamp of the cell balance fet, provides the -1.4v ne eded to detect an open wire. for this reason and for the increased protection, it is not recommended that smaller input series resistors be used. for ex ample, with a 100 input resist or, the voltage across the input resistor drops only 0.1v. this wil l not allow the input open-wire d etection hardware to trigger (although the digital detection of an open wire still works, th e hardware detection automatically turns off the open-wire current). input resistors larger than 1k may be desired to increase the input filtering. this is allowed in the open-wire test, by prov iding an increase in the detection ti me (by changing the owt value.) however, increasing the input re sistors can significantly affec t measurement accuracy. the isl94202 has up to 2a variation in t he input measurement current. this amounts to about 2mv measurement error with 1k resist ors (this error has been factor y calibrated out). however, 10k r esistors can result in up to 20mv measurement errors. to increase the input filtering, the p referred method is t o increase the size of the capacitors. depending on the selection of the input filter components, the internal open-wire comparators may not detect an open-wire condition. this might happen if t he input resistor is small. in this case, the body diode of the cell balance fet may clamp th e input before it reaches the open-wire detec tion threshold. to o vercome this limitation and pr ovide a redundant open-wire detection, at the end of the o pen-wire scan, all input voltages are converted to digital values . if any digital value equals 0 v (minimum) or 4.8v (maximum), the device sets an open error flag indicating an open-wire failure. when an open-wire condition occurs and the open-wire power shu tdown (owpsd) bit is equal to 0, the isl94202 turns off all power fets and the cell balance fets, but does not set the psd output. while in this c ondition, the device continues t o operate normally in all other ways (i.e., the cells are scanned and the current monitored. as ti me passes, the device drops in to lower power modes). notes: 1. voltage drop = 1ma * 1k = 1v. 2. voltage = v f of cb5 balance fet body diode + (1ma * 1k). 3. owpsd bit = 0. 4. this time is 8s in idle and 16s in doze. 5. this 32ms scan rate increases to 256ms in idle and 512ms in d oze. figure 9.18 open-wire test timing vc max - vc min pack cell imbalance pack vc5 open wire cellf threshold pack open wire cleared ~160ms (default) open-wire scan vc8 ow test vc7 ow test vc6 ow test vc5 ow test vc4 ow test vc3 ow test vc2 ow test vc1 ow test voltage scan t ow open bit ~1ms vc6 vc5 vc4 1v ~1.7v no open-wire scans voltage scan reports that vc5 = 0v and vc6 = 4.8v cellf bit default = 20ms 1s 32ms cbal fets turn off ( note 1 ) ( note 2 ) ( note 4 ) ( note 5 )
isl94202 9. open-wire detection fn8889 rev.2.00 page 36 of 89 mar 8, 2017 when an open-wire condition occurs and owpsd = 1, the open flag is set, the isl94202 turns off all power fets, and the cell balance fets and the isl9 4202 sets the psd output port act ive. the device can automatically reco ver from an open-wire conditio n, because the open-wire test is still functional, unless the owpsd bit equals 1 and the psd p in blows a fuse in the pack. if the open-wire test finds that t he open wire has been cleared, then open bit is reset and other tests determine whether condit ions allow the power fets to turn back on. the open-wire test har dware has two limita tions. first, it depe nds on the cellf indicator. if the cell balance maximum voltage delta (cbdu) value is set to high (fffh for example), t hen the device may never detect a cellf condition. the second limitation is that the open-wire test does not happen im mediately. first, a scan must detect a cellf condition. cellf detection happens in a maximum o f 32ms (normal mode) or in a ma ximum of 256ms (doze mode). once cellf is detected, the open-wire test occurs on the next scan, 32ms to 256ms later .
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 37 of 89 mar 8, 2017 10. current and voltage monitoring there are two main automatic p rocesses in the isl94202. the fir st are the current monitor and overcurrent shutdown circuits. the second are the voltage, temp erature, and current analog-to- digital scan circuits. 10.1 current monitor the current monitor is an analog detection circu it that tracks the charge and discharge curren t and current di rection. the current monitor circuit is on a ll the time, except in sleep and power-down modes. the current monitor compares the voltage across the sense resis tor to several different thresholds. these are short-circuit (discharge), overcurrent (discha rge), and overcurrent (charge). if the measured voltage exceed s the specified limit, for a specified duration of time, the isl94202 acts to protect the sy stem, as described in the following section. the current monitor also tracks the direction of the current. t his is a low-level d etection and indicates the presence of a charge or discharge current. if either condition is detected, t he isl94202 sets an appropriate flag. 10.2 current sense the current-sense element is on the high-side of the battery pa ck. the current-sense circuit has a gain x5, x50, or x500. the sens e amplifier allows a very wide range o f currents to be monitored. the gain settings allow a sense resistor in the rang e of 0.3m to 5m. a diagram of the current-sens e circuit is shown in figure 10.19 . there are two parts of the curre nt-sense circuit. the first par t is a digital current monitor ci rcuit. this circuit allows the current to be tracked by an external microcontroller or compute r. the current-sense ampli fier gain in t his current measurement is set by the [cg1:c g0] bits. the 14-bit offset adj usted adc result of the conversion of the voltage across the current-sense resistor is saved to ram, as well as a 12-bit val ue that is used for threshol d comparisons. the offset adjustment is based on a factor y calibration value saved in e eprom. the digital readouts cover the input voltage ranges shown in table 10.3 . table 10.3 maximum curre nt measurement range gain setting voltage range (mv) current range (rsense = 1m) 5x -250 to 250 -250a to 250a 50x -25 to 25 -25a to 25a 500x -2.5 to 2.5 -2.5a to 2.5a
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 38 of 89 mar 8, 2017 the second part is the analog current direction, overcurrent, a nd short-circuit detect mechanisms. this cir cuit is on all the time. during the operation of the overcurrent detection circuit, the sense amplifier gain is automatically controlled. for current direction detection, there is a 2ms digital delay f or getting into or out of either direction condition. this mean s that charge current detection ci rcuit needs to detect an uninterrupted flow of current out of the pack for more than 2ms to indicate a discharge condition. then, the current detector need s to identify that there is a ch arge current or no current for a continuous 2ms to remove the discharge condition. the overvoltage and short-circui t detection thresholds are prog rammable using values in the eeprom. the discharge overcurrent thresholds are shown in table 10.4 . the charge overcurrent thresholds are shown in table 10.5 . the discharge short-circuit thresholds are shown in table 10.6 . figure 10.19 block diagram for overcurrent detect and current mo nitoring 4 + - overcurrent charge detect r sense + - cs1 cs2 coc [occ2:occ0] overcurrent discharge detect programmable thresholds doc [ocd2:ocd0] short-circuit discharge detect programmable thresholds dsc [dsc2:dsc0] ching dching cg1:0 500 5k 50k 250k 250k 14-bit mux programmable thresholds gain select ao2:0 = 9h note: agc sets gain during overcurrent monitoring. cg bits select gain when adc measures current. voltage scan agc [occtb:occ0] [ocdtb:ocdt0] [sctb:sct0] adc 12 + ram register 12-bit pack current programmable detection time address: [8fh:8eh] ram register 14-bit 14-bit adc output value value ao3:ao0 digital cal eeprom voltage select bits address: [abh:aah] direction current detect + 2ms filter polarity control programmable detection time programmable detection time
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 39 of 89 mar 8, 2017 the charge and discharge overcurrent conditions and the discharge short-circuit condition need to be continuous for a period of time before an over current condition is detected. these times are set by individual 12-bit timers. the timers consist of a 10-bit timer value and a 2-bit scale value (see table 10.7 ). table 10.4 discharge overcu rrent threshold voltages ocd setting threshold (mv) equivalent current (a) 0.3m 0.5m 1m 2m 5m 000 4 13.3 8 4 2 0.8 001 8 26.6 16 8 4 1.6 010 16 53.3 32 16 8 3.2 011 24 80 48 24 12 4.8 100 32 106.7 64 32 16 6.4 101 48 ( note 1 )9 6 4 82 49 . 6 110 64 ( note 1 )( note 1 ) 64 32 12.8 111 96 ( note 1 )( note 1 )( note 1 ) 48 19.2 note: 1. these selections may not be reasonable due to sense resistor power dissipation. table 10.5 charge overcurrent threshold voltages occ setting threshold (mv) equivalent current (a) 0.3m 0.5m 1m 2m 5m 000 1 3.3 2 1 0.5 0.2 001 2 6.7 4 2 1 0.4 010 4 13.3 8 4 2 0.8 011 6 20 12 6 3 1.2 100 8 26.6 16 8 4 1.6 101 12 40 24 12 6 2.4 110 16 53.3 32 16 8 3.2 111 24 80 48 24 12 4.8 table 10.6 discharge short-circ uit current threshold voltages dsc setting threshold (mv) equivalent current (a) 0.3m 0.5m 1m 2m 5m 000 16 53.3 32 16 8 3.2 001 24 80 48 24 12 4.8 010 32 106.7 64 32 16 6.4 011 48 160 96 48 24 9.6 100 64 213.3 128 64 32 12.8 101 96 ( note 1 ) 192 96 48 19.2 110 128 ( note 1 )( note 1 ) 128 64 25.6 111 256 ( note 1 )( note 1 ) note 128 51.2 note: 1. these selections may not be reasonable due to sense resistor power dissipation. assumes short-circuit fet turn off in 10ms or less. table 10.7 charge/discharge overc urrent/short-circuit delay time s [occtb:a] [ocdtb:a] [sctb:a] scale value [occt9:0] [ocdt9:0] [sct9:0] delay (10-bit value) 00 0 to 1024s 01 0 to 1024ms 10 0 to 1024s 11 0 to 1024 minutes
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 40 of 89 mar 8, 2017 10.3 overcurrent and short-circuit detection the isl94202 continually monitors current by mirroring the curr ent across a current-sense re sistor (between the cs1 and cs2 pins) to a resistor to ground. ? a discharge overcurrent conditio n exists when the voltage acro ss the external sense resis tor exceeds the discharg e overcurrent threshold, set by the discharge overcurrent thresho ld bits [ocd2:ocd0], for an overcurrent time delay, set by the discharge overcurrent timeout bits [ocdtb:ocdt0]. this cond ition sets the doc bit high. the ld_prsnt bit is also set high at this time. if the cfet bit is 0, then the pow er fets turn off automatically. if the cfet bit is 1, then the external c must control the power fets. ? a charge overcurrent condition exists when the voltage across the external sense resistor exceeds the char ge overcurrent th reshold, set by the charge overcurrent threshold bits [occ2:o cc0], for an overcurrent time delay, set by the discharg e o vercurrent timeout bits [occtb: occt0]. this condition sets the coc bit high. the ch_prsnt bit is also set high at t his time. if the cfet bit is 0 , then the power fets turn off automatically. if the cfet bit is 1, th en the external c m ust control the power fets. ? a discharge short-circuit condit ion exists when the voltage ac ross the external sense resi stor exceeds the discharg e sho rt-circuit threshold, set by the discharge short-circuit thr eshold bits [scd2:scd0], for an overcurrent time delay, set b y th e discharge short-circuit timeout bits [scdtb:scdt0]. this co ndition sets the dsc bit hig h. the ld_prsnt b it is a lso set high at this time. the power fets turn off automatical ly in a short-circuit condition, regardless of the condition of the cfet bit. 10.4 overcurrent and short-ci rcuit response (discharge) once the isl94202 enters the discharge overcurrent protection o r short-circuit protection mode, the isl94202 begins a load monitor state. in the load monitor state, the isl94202 waits th ree seconds and then periodically checks th e load by turning on the ldmon output for 0 to 15ms every 256ms. program the puls e duration with the [lp w3:lpw0] bits in eeprom. when turned on, the recovery circuit outputs a small current (~ 60a) to flow from the device and into the load. with a load present, the voltage on the ldmo n pin is low and the ld_prsnt b it remains set to 1. w hen the load rises to a sufficiently high resistance, the voltage on the ldmon pin rise s above the ldmon threshold and the ld_prsnt bit is reset. when the load has been released for a sufficiently long period of time (two successive load sample periods) the isl94202 recognizes that the co nditions are ok and resets the d oc or dsc bits. if the cfet bit is 0, then the d evice automatically re-enables the power fets by setting the dfet and cfet (or pcfet) bits to 1 (assuming all other conditions are within normal ra nges). if the cfet bit is 1, then the c must turn on the power fets. an external microcontroller can o verride the automatic load mon itoring of the device. it does this by taking control of the load monitor circuit (set the clmon bit = 1) and periodically pulsing the lmon_en bit. when the microcontroller detects that ld_prsnt = 0, the c sets the clr_lerr bit to 1 (to clear the error condition an d reset the doc or dsc bit) and sets the dfet and cfet (or pc fet) bits to 1 to turn on th e power fets.
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 41 of 89 mar 8, 2017 10.5 overcurrent response (charge) once the isl94202 enters the cha rge overcurrent protection mode , the isl94202 begins a charger monitor state. in the charger monitor state, the isl94202 periodically checks the cha rger connection by turning on the chmon output for 0ms to 15ms every 256ms. program the use duration with the [cpw3:cp 0] bits in eeprom. when turned on, the r ecovery circuit check s the voltage on the chmon pin. with a charger present, t he voltage on the chmon pin is high (>9v) and the ch_prsnt bit remains set to 1 . when the charger conn ection is removed, the voltage on the chmon pin falls below the chmon threshold and th e ch_prsnt bit is reset. when the charger has been released for a sufficiently long period of time (two successive sample periods), the isl94202 recognizes that the conditions are ok and clear s the coc bit. if the cfet bit is 0, the device automatically re-enables the power fets by setting the dfet and cfet (or pcfet) bits to 1 (assuming all other conditions are within normal ranges). if the cfet bit is 1, then the c must turn on the power fets. an external microcontroller can o verride the automatic charger monitoring of the device. it doe s this by taking control of the load monitor circuit (set the ccmon bit = 1) and periodica lly pulsing the cmon_en bit. when the microcontroller detects that ch_prsnt = 0, the c sets the clr_cerr bit to 1 (to clear the error condition an d reset the coc bit) and sets the dfet and cfet (or pcfet) bits to 1 to turn on the power f ets. sense coc bit overcurrent i occ normal operation mode normal operation mode notes: 1. when cfet = 1, coc bit is reset when the clr_cerr is set to 1. 2. when cfet = 0, coc is reset by the isl94202 when the conditi on is released figure 10.20 charge overcurrent protection mode - event diagram protection mode cfet coc bit (cfet = 0) (cfet = 1) t occt chmon pin v chmon charger still charger removed sample rate set by isl94202 when cfet = 0 cmon_en sample rate set by microcontroller when cfet = 1 and ccmon = 1 (from c) connected current ( note 1 ) ( note 2 )
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 42 of 89 mar 8, 2017 10.6 microcontroller overcurrent fet control protection if any of the microcontroller override bits (cscan, cfet, cl mon, ccmon, or cbal) are set to 1 and the microcontroller does not send a valid slave byte to the isl9420 2 within the watchdog timeout period, then the microcontroller control bits are all reset, the device turns of f the power fets and the balance fets, and the int output provides a 1s pulse one time per second. notes: 3. when cfet = 1, cfet, dfet and pcfet are controlled by extern al c. when cfet = 0, cfet, dfet and pc fet are controlled automatical ly by the isl94202. 4. when cfet = 1, doc and dsc bits are reset by setting the clr _lerr bit. when cfet = 0, doc and dsc are reset by the isl94202 when the condition is released. 5. pcfet turns on if any cell voltage is less than lvchg thresho ld. otherwise cfet turns on. 6. dfet does not turn on if any cell is less than the uv thresho ld, unless the dfoduv bit is set. dfet v ss o.c. protection v ocd normal operation mode v ocd normal battery v dsc v dsc normal short t sc ldmon pin lmon_en v ldmon t ocdt doc ld_prsnt load not released load released (external doc dsc (stand alone) v cs (from c) cfet pcfet voltage sleep note 3 note 3 note 3 note 4 note 4 note 5 note 5 note 5 note 5 note 6 note 6 figure 10.21 discharge overcurrent protection mode - event diagr am no current for 2x idle/mode mode time + sleep mode time sample rate set by c when cfet = 0 sample rate is set by c. when cfet = 1 and clmon = 1 3s 3s control)
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 43 of 89 mar 8, 2017 10.7 voltage, temperature, and current scan the voltage scan consists of the monitoring of the digital repr esentation of the current, cell voltages, temperatures, pack voltage, and regulator voltage. this scan occurs once every 32m s, 256ms, or 512ms (depending on the mode of operation, see figure 10.22 ). the temperature, pack voltage, and regulator voltage are sca nned only every fourth scan. the open wire is scanned every 32nd scan as l ong as the cellf condition exist s. after each measurement scan, the isl94202 performs an offset ad justment and stores the values in ram. after the values are stored, the stat e machine executes co mpare operations that determine if the pack is operating within limits. see figure 10.22 for details on th e scan sequence. during manufacture, intersil prov ides calibration values in the eeprom for each cell voltage reading. when there is a new conversion for a particular vol tage, the calibration is applied to the conversion. notes: 7. the open-wire test performed every 32 voltage scans, if cellf = 1, just prior to the scan. 8. fets turn off immediately if there is an error, but they do n ot turn on until the end of the voltage scan (at fet update if everything else is ok). an exc eption to this is when a device w akes up when connected to a load. in this case, the fets turn on immediately on wake-up, then a scan begins. 9. the voltage scan can be turned off by an external microcontro ller by setting the cscan bit. this bit is monitored by the watchdog timer, so if an external microcontroller stops communi cating with the isl94202 for more than the wdt period, this bit is automatically reset and the scan resumes. mux sel settling time adc convert current/voltage monitor (every cycle) cell1 cell2 cell3 cell8 isl94202 cell voltage monitoring 32ms 256ms isl94202 pack voltage monitoring cell1 cell2 32ms 256ms mux sel settling time adc convert isl94202 temperature monitoring xt1 xt2 current/voltage/temperature monitor (every 4th cycle) current select/settling time isl94202 current monitoring offsets/cb calculat ions/open wire detect open wire ~100s ~500s v batt /16 ov/uv/uvlo detect/fet update/add offsets/cb calculations/open wire detect ov/uv/uvlo detect/fet update/add temperature calculations it rgo/2 512ms 512ms low power state low power adc convert mux sel settling time adc convert current turn on adc current cell1 cell1 open wire cell7 1ms 1ms ~50s figure 10.22 cell voltage, current, temperature scanning int_scan bit int_scan bit ~1.3 ms ~1.7 ms
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 44 of 89 mar 8, 2017 10.8 cell voltage monitoring the circuit that monitors the input cell voltage multiplies the cell voltage by 3/8. the adc converts this voltage to a digita l value, using a 1.8v in ternal reference. the adc produces a cali brated 14-bit value, but only 12 bits are stored in the cell registers (see figure 10.23 .) in manufacturing, each cell voltage is calib rated at 3.6v per c ell and at +25c. this calibrated value is used for all subsequent voltage threshold comparisons. the isl94202 has two different overvoltage and undervoltage lev el comparisons, ovlo/uvlo and ov/uv. while both use the adc converter output val ues and a digital comparator, t he responses are different. the ovlo and uvlo levels are meant to be secondary thresholds above and below the ov and uv thresholds. 10.8.1 uvlo and ovlo because they provide a secondar y safety condition, ovlo and uvl o can cause the pack t o shut down, either permanently, as in the case of a n ovlo when the psd pin connect s to an external fuse; or severely, as in the case of an uvlo when the device powers down and requires connection to a charger to recover. the ovlo condition can be overridde n by setting the ovlo thresh old to fffh or by an external c setting the cscan bit to override the intern al automatic scan, then turnin g on the cfet. however, if the c takes permanent control of the scan, the c need s to take over the scan for all cells and all control function s, including comparisons of the cell voltage to ov and uv thresholds, m anaging time delays, and controlling all ce ll balance functions. the uvlo response can be overridd en by setting the uvlo thresho ld to 0v. the device can respond to the uvlo condition by entering the power-do wn mode (set uvlopd in eeprom to 1) or by turning off the fets and setting the uvlo bit (uvlopd = 0). when the uvlopd bit is set to 1 (indicating that the isl94202 should power down during a uvlo condition) and the cfet bit is set t o 1 (indicating that the c is in contr ol of the fets), the automat ic uvlo control forces a power-down condition, overriding the c fet control. the uvlo and ovlo detection both have delays of 5 sample cycles (typically 160ms) to prevent noise generated entry into the mode. the ovlo and uvlo val ues are each set by 12 -bit values in eepro m. the ovlo has a recovery threshold of ovr and uvlo has a recover y threshold of uvr (if t he response overrides have been set). if the response o verrides are not set, then the recovery thresholds are usua lly irrelevant; for example, when the uvlo forces the device into a power-down condition or the ovlo condition caused a psd controlled fuse to blow. 10.8.2 uv, ov, and sleep uv, ov, and slp thresholds are s et by individual 12-bit values. uv and ov recovery thresholds are set by individual 12-bit valu es. the voltage protection scan occu rs once every 32ms in normal op eration. if there has been no activity (no charge or discharge current) detected in a programmable period of 1 to 16 minutes, then the scan occurs every 256ms (idle mode). if no charge or discharge condition has been det ected in idle mode for the programmable pe riod, then the scan occurs every 512ms. if an overvoltage, undervoltage, or sleep condition is detected and is pending, the scan rat e remains unchanged. it can take longer to detect the fault condition in idle or doze modes . the scan rate is determined by the mode of operation and the mode of operation is determined solely by the time since pa ck charge/discharge current was detected.
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 45 of 89 mar 8, 2017 during a scan, each cel l is monitored for overvoltage, undervol tage, and sleep voltage. the voltage will also be converted to an adc value a nd be stored in memory. if, during the scan, a voltage i s outside the set limit, then a timer starts. there is one timer for all of the cells. if the condition remains on any cell or combination of cells for the d uration of the time period, an error condition exists. this sets the appropriate flag and not ifies the protection circuitry to take action (if automatic action is enabled). the timeout delays for ov, uv, and sleep are each 12-bit values stored in eeprom (see table 10.8 ). the control logic for overvo ltage, undervoltage, and sleep cond itions is shown in table 10.8 , figure 10.24 and figure 10.25 on page 48 . figure 10.23 block diagram of cell voltage capture table 10.8 ov, uv, sleep delay times scale value delay (10-bit value) 00 0 to 1024s 01 0 to 1024ms 10 0 to 1024s 11 0 to 1024min input mux/ level digital cal eeprom 12 voltage buffer ? vc0 vc1 shifter vc7 vc8 voltage buffer ram register address: [91h:90h] + 2(n-1); [ao3:ao0] (x 3/8) 1.8v vss ram register 12-bit value 14-bit value 14-bit adc output cell voltage trim address address: [abh:aah] voltage select bits 14-bit adc (n = cell number)
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 46 of 89 mar 8, 2017 10.9 overvoltage detection/response the device needs to m onitor the voltage on each battery cell (v cn ). if for any cell, [v cn - vc(n-1)] > v ov for a time exceeding t ov , the device sets an ov flag. t hen (if cfet = 0), the isl94202 turns the charge fet off, by setting the cfet bit to 0. once the ov fla g is set the pack has entered o vercharge protection mode. the status of the discharge fet remains unaffected. the charge fet remains off unt il the voltage on the overcharged cell drops back below a recovery level, v ovr , for a recovery time period, t ovr . the t ovr time equals the t ov time. the detection timer and recovery timer are asynchronous to the voltage threshold. as a result, a setting of 1s can result in a delay time of 1s to 2s, depending on when the ov/ovr is detecte d. for a setting of 1000ms, th e detection time will be within 1ms. the device further continues to monitor the battery cell voltag es and is released from overcharge protection mode when [v cn - vc(n-1)] < v ovr for more than the overcharge release time, for all cells. when the device is released from overcharge protection mode, th e charge fet is automatical ly switched on (if cfet = 0). when the dev ice returns from overcharge protection mode, th e status of the discharg e fet remains unaffected. during charge, if the voltage on any cell exceeds an end-of-cha rge threshold (eocs), then a n eochg bit is set and the eoc output is pulled low. t he eochg bit and the eoc output resume normal conditions w hen the voltage on all cells drops back below the [eocs - 117mv] threshold. there is also an overvoltage lockout. when this level is reache d, an ovlo bit is set, the psd o utput is set, and the charge fet or precharge fet is immediately turned off (by setting the cfet or pcfet bit to 0). the psd output can be used to blow a fuse to protect t he cells in the pack. if, during an ov condition, the cfet bit is set to 1, the mi crocontroller must control bot h turn off and turn on of the charge and precharge power fets. this does not apply to the ovl o condition. the device includes an option to turn the charge fet back on in an overvoltage condition, if there is discharge current flowing out of the pack. this option is set by the cfodov (cfet on during overvoltage) flag stored in eeprom. then, if the discharge current stops and there is still an over charge condition on the cell, the device again disables the cha rge fet.
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 47 of 89 mar 8, 2017 vcn ov bit normal operation mode overcharge v ov v ovr t ov protection mode pack charge t ovr dflg set dflg reset cfet figure 10.24 overvoltage protection mode-event diagram dfet veoc eoc pin v ovlo psd pin ovlo bit sd pin eochg bit overvoltage lock-out protection mode normal operation mode current discharge cflg reset cfodov flag = 1 allows cfet to turn on during ov, if discharging
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 48 of 89 mar 8, 2017 10.10 undervoltage detection/response if v cn < v uv , for a time exceeding t uvt , the cells are said to be in an overdischarge (undervoltage) s tate. in this condition, the isl94202 sets a uv bit. if the cfet bi t is set to 0, the isl94202 also switches the discharge fet off (by setting the dfet bit = 0). while any cell voltage is less than a low voltage charge thresh old, and if the pcfete bit is set, the pcfet output is turned on instead of the cfet output. t his enables a precharge conditi on to limit the charge curre nt to undervoltage cells. from the undervoltage mode, if t he cells recover to above a v uvr level for a time exceeding t uvt plus three seconds, the isl94202 pulses the ldmon output once every 256ms and looks for the absence of a load. the pulses are of programmable duration (0ms to 15m s) using the [lpw3:lpw0] bits. during the pulse period, a small current (~60a) is output into the load. if there is no load, then the ldmon volta ge will be higher than the rec overy threshold of 0.6v. when the load has been rem oved and the cells are above the undervolt age recovery level, the isl942 02 clears the uv bit and, if cfet = 0, turns on the discharge fet and resumes normal operation. note, the t uv detection timer and t uvr recovery timer are asynchronous to the voltage threshold. as a result, a setting of 1s can result in a delay time of 1s to 2s (and a recovery time of 3s to 4s), depending on when the uv/uvr is detected. for a setting of 1000ms, the detection time will be within 1ms. figure 10.25 undervoltage protection mode-event diagram vc uv bit t uv v uvr v uv i pack discharge lmon_en bit ldmon pin v ldmon dfet bit ld_prsnt bit v sl t sl discharge t uv cfet bit in_slp bit sleep charge cmon_en bit chmon pin v wkupl v wkupc pcfet bit (starts looking for charger/load connect) dfet on if charging and dfoduv bit is set if pcfete set, pcfet turns on here, not cft v lvch uv bit (cfet = 1) (cfet = 0) v uvlo uvlo bit reset when microcontroller writes clr_lerr bit = 1 (from c) t uv +3s dfet remains set if uvlopd = 0 uvlo set if uvlopd = 0 if uvlopd = 1 and cfet = 0 or 1, device powers down dfet on if charging and dfoduv bit is set sampling for load release (looking for tool trigger release) (clmon pulses) (clmon bit = 1) microcontroller only. load released overdischarge protection mode overdischarge protection mode t uv +3s wake up charge connect if charge voltage connected and cfet = 1
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 49 of 89 mar 8, 2017 if any of the cells drop below a sleep threshold (vcn < v slp ) for a period of time (t slt ), the device sets the sleep bit and (if cfet = 0), the isl94202 turns off both fets (dfet and cfet = 0 ) and puts the pack into a sleep mode by setting the sleep bit to 1. if the cfet b it is set, the device does not go to sleep. there is also an undervoltage lockout condition. this is detect ed by comparing the cell volt ages to a programmable uvlo threshold. when any cell voltage d rops below the uvlo threshold and remains below the threshold for five voltage scan periods (~160ms), a uvl o bit is set and the sd output pin goes active. if uvlo pd = 0 and cfet = 0, the dfet i s also turned off. if uvlopd = 1, then the isl94202 goes into a power- down state. if the cfet bit is set to 1, the microcontroller must both t urn off and turn on the discharg e power fets and control the sleep and power-down conditions. the device includes an option to turn the discharge fet back on in an undervoltage condition, if there is a charge current flowing into the pack. this option is set by the dfoduv (dfet o n during undervoltage) flag stored in eeprom. then, if the charge current stops and there is still an undervoltage condition on the cell, the devi ce again disables the discharge fet. 10.11 temperature monitoring/response as part of the normal voltage scan, the isl94202 monitors both the temperature of the device and the temperature of two external temperature sensors. external temperature 2 can be used to monitor the temperature of the fets, instead of the cells, by setting the xt2m bit to 1. the temperature voltages have two gain settings (the same gain for all temperature inputs). fo r external temperatures, a tgain bit = 0, sets th e gain to 2x (full scale input voltage = 0 .9v). a tgain bit = 1 and sets t he gain to 1x (full scale input voltage = 1.8v). see figure 10.26 . the default temperature gain set ting is x2, so the temperature monitoring circuit of t gain = 0 (gain = 2) is preferred. this configuration has other advantag es. the temperature response is more linear and covers a wider temperature range before nearing the limits of the adc reading. the internal temperature reading converts from voltage to tempe rature using (eq. 1) and (eq. 2) : if the temperature of the ic (in ternal temp) goes above a progr ammed over-temperature threshold, then the isl94202 sets an over-temperature fl ag (iot), prevents cel l balancing and tur ns off the fets . tgain 1 = inttemp mv ?? 1000 ? 0.92635 ------------------------------------------------------ - 273.15 Cictemp ? c ?? = (eq. 1) tgain 0 = inttemp mv ?? 1000 ? 1.8527 ------------------------------------------------------ - 273.15 Cictemp ? c ?? = (eq. 2) thermistors: 10k, 10k 10k xt2 pin xt1 pin tempo pin 22k 22k +80c = 0.153v +50c = 0.295v +25c = 0.463v 0c = 0.710v -40c = 0.755v xt2 pin xt1 pin tempo pin 82.5k 82.5k +80c = 0.050v +50c = 0.120v +25c = 0.270v 0c = 0.620v -40c = 1.758v murata xh103f t gain = 0 (gain = 2) t gain = 1 (gain = 1) figure 10.26 external t emperature circuits
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 50 of 89 mar 8, 2017 cell balance over-temp sample mode discharge over-temp charge over-temp xt1cuts xt2>cuts or xt1>duts xt2>duts or xt1>cbuts xt2>cbuts set cut bit = 1 set dut bit = 1 set cbut bit = 1 cfet = 1 cfet = 1 cfet = 1 charge shutdown turn off cfet discharge shutdown turn off dfet balance shut down turn off balancing figure 10.27 temperature management state machine xt1>cotr xt2>cotr or xt1>dotr xt2>dotr or xt1>cbotr xt2>cbotr xt2m = 0 cell balance discharge charge xt1 isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 51 of 89 mar 8, 2017 10.11.1 over-temperature if the temperature of either of the external temperature sensor s (xt1 or xt2), as determined b y an external resistor and thermistor, goes below any of the thresholds (charge, discharge , and cell balance as set by internal eeprom values), indicating an over-temperature condition, the isl94202 sets the corresponding over-temp flag. if the automatic responses are en abled (cfet = 0), the charge over-temperature (cot) or discharge over- temperature (dot) flag is set and the corresponding charge or d ischarge fet is turned off. for series fet applications, cot will not shut off cfet during discharge regardless of cfet setting. if the cell balance over-temperature (cbot) flag is set, the device turns off the balancing outputs and prevents cell balancing while the condition exists. if the automatic responses are disabled (cfet = 1), then the i sl94202 only sets the flags and an external microcontroller responds to the condition. an exception to the above occurs if the xt2 sensor is configure d as a fet temperature indi cator (xt2m = 1). in this case, the xt2 is not compared to the cell balance temperature t hresholds, it is used on ly for power fet control. 10.11.2 under-temperature if the temperature of either of the external temperature sensor s (xt1 or xt2), as determined b y an external resistor and thermistor, goes above any of the thresholds (charge, discharge , and cell balance as set by internal eeprom values), indicating an under-temperature condition, the isl94202 sets th e corresponding under-temperature flag. if the xt1 automatic responses ar e enabled (cfet = 0), then the charge under-temperature (cut) or discharge under-temperature (dut) flag is set the corresponding charge or discharge fet is turned off. for series fet applications, cut will not shut o ff cfet during discharge regar dless of cfet setting. if the cell balance under-temperature (cbut) flag is set, the device turns off cell balancing outputs and prevents cell balancing. if the xt2 automatic responses are disabled (cfet = 1) then the isl94202 only sets the f lags and an external microcontroller responds to the condition. an exception to the above occurs if the xt2 sensor is configure d as a fet temperature indi cator (xt2m = 1). in this case, the xt2 is not compared to the cell balance temperature t hresholds. it is used only for power fet control). for both xt1 and xt2, when the temperature drops back within a normal operating range, the over or under-temperature condition is reset.
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 52 of 89 mar 8, 2017 10.12 microcontroller read of voltages an external microcontroller can read the value of any of the in ternally monitored voltages independently of the normal voltage scan. to do this requires that the c first set the cs can bit. this stops the intern al scan and starts the watchdog timer. if the c maintai ns this state, then communication must continue and the c must manage all voltage and current pack control operations as well as implement the cell balance a lgorithms. however, if the c scan bit remains set for a short period of time, the device continues to monitor voltages and control the pack operation. once the cscan bit is set, the e xternal c writes to register 85h to select the desired voltage and to start the adc conversion (set the adcstrt bit to 1 to start an adc conversi on). once the conversion is complete, the results are read from the adc registers [adcd:adc 0]. the result is a 14-bit valu e. the adc conversion takes about 100s or the c can poll the i 2 c link waiting for an ack to indicate that the adc conversion i s complete. if the cscan bit is set when th e isl94202 internal scan is sch eduled, then the internal scan pauses until the cscan bit is cleared and the interna l scan occurs immediately. reading an adc value from the c requires the following sequence (and time) to complete: to sample more than one time (for averaging), repeat steps 2 th rough 5 as many times as des ired. however, if this is a continuous operation, care must be taken to monitor other pack functions or to pause long enough for the isl94202 internal operations to collect data to cont rol the pack. a burst of five measurements takes about 1.8ms. table 10.9 c controlled measu rement of individual voltages step operation number i 2 ccycles time at 400khz i 2 c clk (ea.) (s) time (cumulative) (s) 1 set cscan bit 29 72.5 72.5 2 set voltage and start adc 29 72.5 145 3 wait for adc complete n/a 110 255 4 read register ab 29 72.5 327.5 5 read register aa 29 72.5 410 6 clear cscan bit 29 100 472.5
isl94202 10. current and voltage monitoring fn8889 rev.2.00 page 53 of 89 mar 8, 2017 10.13 voltage conversions to convert from the digital value stored in the register to a real world voltage, the following conversion equations should be used. the term hexvalue 10 means the binary to decimal conversion of the register value. 10.13.1 cell voltages cell voltage = the cell voltage conversion equat ion is also used to set the voltage thresholds. 10.13.2 pack current pack current = gain is the gain setting in regis ter 85h, set by the [cg1:cg0] bits. senser is the sense resistor value in ohms. this pack current read ing is valid only when the current direct ion indicators show that ther e is a charge or discharge current. if the curren t is too low for the indicators to show c urrent flowing, then use the 14-bit value to estimate the current. see 14-bit register on page 53. 10.13.3 temperature temperature = equation 5 converts the register value to a voltage, but the temperature then is converted to a t emperature depending on the external arrangement of thermistor and resistors. see temperature monitoring/response on page 49 . 10.13.4 14-bit register if hexvalue 10 is greater than or equal to 8191, then: 14-bit value = if hexvalu e 10 is less than 8191, then: 14-bit value = on ce the voltage value is obtaine d, if the measurement is a cel l voltage, then the value should be multiplied by 8/3. a temperature value is used as-is , but the voltage value is con verted to temperature by including the external temperature circuits into the conversion. to determine pack curre nt from this 14-bit value requires the f ollowing computations. first, if both current direction flags show zero current, then the external controller must ap ply an offset. measure the 14- bit voltage when there is a pack current of 0. then subtract th is offset from the 14-bit curr ent-sense measurement value and take the absolute value of the result. if either of the cur rent direction flags indicate a current, then do not subtract t he offset value, but use the 14-bit value directly. in either case , divide the 14-bit voltage value by the current-sense gain and the current-sense re sistor to arrive at the pack current. hexvalue 10 1.8 8 ?? 4095 3 ? ------------------------------------------------------- (eq. 3) hexvalue 10 1.8 ? 4095 gain ? senser ? -------------------------------------------------------- - (eq. 4) hexvalue 10 1.8 ? 4095 ---------------------------------------------- (eq. 5) hexvalue 10 16384C ?? 1.8 ? 8191 ----------------------------------------------------------------------- - (eq. 6) hexvalue 10 1.8 ? 8191 ---------------------------------------------- (eq. 7)
isl94202 11. microcontroller fet control fn8889 rev.2.00 page 54 of 89 mar 8, 2017 11. microcontroller fet control the external microcontroller can override the device control of the fets. with the cfet bit set to 1, the external microcontroller can turn the fets on or off under all condition s except the following: ? if there is a discharge short-c ircuit condition, the device tu rns the fets off. the external microcontroller is responsible f or turning the fets back on once th e short-circuit condition clear s. ? if there is an internal over-temperature condition, the device turns the fets off. the exter nal microcontroller is responsibl e for turning the fets back on once the temperature returns to within normal operating lim its. ? if there is an overvoltage lockout condition, the device turns the charge or precharge fets off. the external microcontroller is responsible for turning the fets back on, once the ovlo conditi on clears. this assumes that the psd output has not blown a fus e to disable the pack. ? if there is an open-wire detection, the device turns the fets off. the external microcontroller is responsible for turning th e fet back on. this assumes that the open wi re did not cause the psd outpu t to blow a fuse to disable the pack. ? if the fetsoff input is high, the fets turn off and remain off . the external c is responsible for turning the fets on once the fetsoff co ndition clears. ? if there is a sleep condition, the device turns the fets off. on wake up, the microcontroller is responsible for turning on the fets. the microcontroller can also co ntrol the fets by setting the cscan bit. however, this also stops the scan, requiring the microcontroller to man age the scan, voltage comparisons, fet control, and cell balance. while t he cscan bit is set to 1, the only operations controlled by the device are: ? discharge short-circuit fet cont rol. the external c cannot ov erride the turn off of the fets during the short-circuit. ? fetsoff external control. the f etsoff pin has priority on cont rol of the fets, even when the microcontroller is managing the scan. ? in all other cases, the microcontroller must manage the fet co ntrol, because it is also managing the voltage scan and all comparisons.
isl94202 12. cell balance fn8889 rev.2.00 page 55 of 89 mar 8, 2017 12. cell balance at the same rate as the scan of the cell voltages , if cell bala ncing is on, the system checks for proper cell balance conditio ns. the isl94202 prevents cell balancing if proper temperature, cur rent, and voltage conditions are not met. the cells only balanc e during a cbon time period. when the cboff timer is running, the cell balance is off. three addi tional bits determine whether the balancing happens only during charge, only during discharge , during both charge and dischar ge, during the end of charge condition, or not at any time. ? the cell balance circuit depends on the 14-bit adc converter b uilt into the device and the re sults of the cell voltage scan (after calibration). ? the adc converter loads a set of registers with each cell volt age during every cell voltage measurement. ? at the end of the cell voltage measurement scan, the isl94202 updates the minimum (celmin) and maximum (celmax) cell voltages. ? after calculating the celmin a nd celmax values, all of the cel l voltages are compared with the celmin value. when any of the cells exceed celmin by cbdl (the minimum cb delta vo ltage), a flag is set in ram indicating that the cell needs balancing (this is the cbnon bit). ? if any of the cells exceed the lowest cell by cbdu (maximum cb delta voltage) then a flag is set indicating that a cell voltage failure occurred (cellf). ? when the cellf flag indicates that there is too great a cell t o cell differenti al, the balancing is turned off. ? if celmax is below cbmin (all the cell voltages are too low fo r balancing) then the cbuv bit is set and there will be no cell balancing. cell balance does not start again until the cbm in value rises above (cbmin + 117mv). when this happens, the isl94202 cl ears the cbuv bit. ? if the celmin voltage is greater than the cbmax voltage (all t he cell voltages are too high for balancing) then the cbov bit is set and there will be no cell balancing. cell balancing does not start again until the cbmax value drops below (cbmax - 117mv). when this happe ns, the isl94202 clears the cbov bit. ? a register in eeprom (cells) identifies the number of cells th at are supposed to be present so only the cells present are used for the cell balance operatio n. note: this is also used in the cell voltage scan and open-wire detect operation. ? there are no limits to the number of cells that can be balance d at any one time, because the balancing is done external to th e device. ? the cell balance block updates at the start of the cell balanc e on period to determine if bal ancing is needed and that the ri ght cells are being balanced. the ce lls selected at this time will be balanced for the duration of the cell balance period. ? the cell balance is disabled if any external temperature is out of a programmed range set by cbuts (cell balance under temperature) and cbots (cell balance over-temperature). ? the cell balance operation can be disabled by setting the cell balance during charge (cbdc), the cell balance during discharge (cbdd), and the cell b alance during end-of-charge (cb _eoc) bits to zero. see table 12.10 on page 56 . ? cell balancing turns off when set to balance in the charge mod e and there is no charging current detected (see cb_eoc exception below). ? cell balancing turns off when set to balance in the discharge mode and there is no discharge current detected (see cb_eoc exception below). ? if cell balancing is set to operate during both charge and dis charge, then isl94202 balances while there is charge current or discharge current, but does not balance when no current flow is detected (all other limiting factors continue to apply). see cb_eoc exception in the following. ? the cb_eoc bit provides an excep tion to the cell balance curre nt direction limit. when the cb_eoc bit is set, balancing occurs while an end of charge condition exists (eoc bit = 1), r egardless of current flow. thi s allows the isl94202 to drain high voltage cells when the charge is complete. this speeds the balancing of the pack, especially when there is a large capacity differential between cells. once the end of charge con dition clears, the cell balance operation returns to normal programming. ? balance is disabled by asserti ng the fetsoff external pin.
isl94202 12. cell balance fn8889 rev.2.00 page 56 of 89 mar 8, 2017 ? the cell balance outputs are on only while the cell balance on timer is counting down. this is a 12-bit timer. the cell balan ce outputs are all off while the cell balance off timer is countin g down. this is also a 12-bit timer. the timer values are set a s in table 12.11 . table 12.10 cell balance truth table (see figure 12.28 ) cb_eoc bit eoc pin cbdc ching cbdd dching enable 0 1 x 1 000 0 0 0 1 x 1 000 1 0 0 1 x 1 001 0 0 0 1 x 1 001 1 1 0 1 x 1 010 0 0 0 1 x 1 010 1 0 0 1 x 1 011 0 0 0 1 x 1 011 1 0 0 1 x 1 100 0 0 0 1 x 1 100 1 0 0 1 x 1 101 0 0 0 1 x 1 101 1 1 0 1 x 1 110 0 1 0 1 x 1 110 1 0 0 1 x 1 111 0 1 0 1 x 1 111 1 0 1 0 xxx x 1 table 12.11 cbon and cboff times scale value time (10-bit value) 00 0 to 1024s 01 0 to 1024ms 10 0 to 1024s 11 0 to 1024min
isl94202 12. cell balance fn8889 rev.2.00 page 57 of 89 mar 8, 2017 12.1 c control of cell balance fets to control the cell balance fets, the external microcontroller first needs to set the ccbal b it to turn off the automatic cell balance operation. to turn on a cell balance fet, the c needs to turn on the cell balance output fet using the c ell balance cont rol register 84h. in this regi ster, each bit correspo nds to a specific cell balance output. with the cell balance outputs sp ecified, the microcontroller se ts the cbal_on bit. this turns on the cell balance output control circuit. 12.2 cell balance fet drive the cell balance fets are driven by a current source or sink of 25a. the gate voltage on the externals fet is set by the gate to source resistor. this resistor should be set such that the gate voltage does not exceed 9v. an external 9v zener diode across the gate to source resistor can help to prevent overvoltage conditions on the cell balance pin. the cell balance circuit connection is shown in figure 12.29 on page 58 . figure 12.28 cell balance operation cberr cb8 driver cb7 driver cb6 driver cb5 driver cb4 driver cb3 driver cb2 driver cb1 driver enable 6 7 3 5 4 2 cell5 voltage - cellmin > cbmindv or [cb5on] cell4 voltage - cellmin > cbmindv or [cb4on] cell3 voltage - cellmin > cbmindv or [cb3on] cell6 voltage - cellmin > cbmindv or [cb6on] cell7 voltage - cellmin > cbmindv or [cb7on] cell8 voltage - cellmin > cbmindv or [cb8on] cell2 voltage - cellmin > cbmindv or [cb2on] cell1 voltage - cellmin > cbmindv or [cb1on] casc cb off timer is counting cbov bit dching bit cbdd ching bit cbdc bit cb_eoc eoc pin fetsoff pin sd pin cellf bit open bit cbut bit cbot bit cbuv bit 1
isl94202 12. cell balance fn8889 rev.2.00 page 58 of 89 mar 8, 2017 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vc0 cb7 cb6 39 vc8 cb8 100 figure 12.29 cell balance drive c ircuits and cell connection opt ions 10k 316k 39 1k 470nf 47nf 10k 316k 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 1k 10k 316k 47nf 39 10k 316k 47nf cb5 cb4 cb3 cb2 cb1 1k 47nf vss cb6on cb7on cb8on cb5on cb4on cb3on cb2on cb1on vss 10v 10v 10v 10v 10v 10v 10v 10v 4m 4m 4m 4m 4m 4m 4m 4m isl94202 25a 25a 25a 25a 25a 25a 25a 25a cbal_on enable 1k
isl94202 13. watchdog timer fn8889 rev.2.00 page 59 of 89 mar 8, 2017 13. watchdog timer the i 2 c watchdog timer prevents an external microcontroller from init iating an action that it cannot undo through the i 2 c port, which can result in poor or une xpected operation of the pack. the watchdog timer is normally in active when ope rating the devi ce in a stand-alone operation. w hen the pack is expected to have a c along with the isl942 02, the wdt is act ivated by sett ing any of the following bits: cscan, ccmon, clmon, ccbal, cfet, eeen. when active (an external c is a ssumed to be connected), the ab sence of i 2 c communications for the watchdog timeout period causes a timeout event. the isl94202 needs to see a start bit a nd a valid slave byte to restart the timer. the watchdog timeout signal turn s off the cell balance and powe r fet outputs, reset s the serial interface, and pulses the int output once per second in an attempt to get the microcontroller to respond. if the int is unsuccessful in restarting the communication interface, the par t operates normally, except the power fets and cell balan ce fets are forced off. the isl94202 remains in this condition until i 2 c communications resumes. when i 2 c communication resumes, the cs can, ccmon, clmon, cfet, and eeen bits are automatically cleared and the ccbal bit remains set. the power fets and cell balance fets turn on, if conditions allow.
isl94202 14. power fet drive fn8889 rev.2.00 page 60 of 89 mar 8, 2017 14. power fet drive the isl94202 drives the power fets gates with a voltage higher than the supply voltage by using external capacitors as part of a charge pump. the capacito rs connect (as shown in figure 1.2 on page 3 ) and are nominally 4.7nf. the charge pump applies approximately (v dd * 2) voltage to the gate, alt hough the voltage is clamped at v dd + 16v. the power fet turn-on times ar e limited by the capacitance of the power fet and the current supplied by the charge pump. the power fet turn-off times are limited by the capacitance of the power fet and the pull-down current of the isl94202. the isl94202 provides a pull-down cur rent for up to 300s. this should be long enough to discharge any fet capacitance. table 14.12 shows typical turn-on and turn -off times for the isl94202 unde r specific conditions. table 14.12 power fet gate control (typical) parameter conditions typical power fet gate turn-on current dfet, cfet, pcfet charge pump caps = 4.7nf 32khz 5ma, pulses, 50% duty cycle power fet gate turn-on time 10% to 90% of final voltage v dd = 28v; dfet, cfet = irf1404 pcfet = fdd8451 160s 160s power fet gate turn-off current c fet, cfet, pcfet 13ma (cfet, pc fet) 15ma (dfet) power fet gate turn-off pulse width pulse duration 300s power fet gate fall time 90% to 10% of final voltage v dd = 28v; dfet: irf1404 cfet: irf1404 pcfet: fdd8451 6s 6s 2s
isl94202 15. general i/os fn8889 rev.2.00 page 61 of 89 mar 8, 2017 15. general i/os there is an open-drain output (sd ) that is pulled up to rgo (using an external resistor) and ind icates if there are any error conditions, such as overvoltage, u ndervoltage, over-temperature , open input, and overcurrent . the output goes active (low) when there is any ce ll or pack failure condition. the output returns high when all error conditions clear. there is an open-drain output (eoc ) that is pulled up to rgo (using an externa l resistor) and ind icates that the cells have reached an end of charge state. the output goes active (low) wh en all cell voltages are above a threshold specified by a 12-bi t value in eeprom. the output retur ns high, when all cells are be low the eoc threshold. factory programmable options offer inverse polarity of sd or eoc . please contact automotive marketing if there is interest in either of these options. the psd pin goes active high, when any cell voltage reaches the ovlo threshold (ovlo flag). optionally, psd also goes high if there is a voltage diffe rential between any two cells t hat is greater than a specified limit (cellf flag) or if there is an open-wire condition. this pin can be used for blo wing a fuse in the pack or as an interr upt to an external c. an input pin (fetsoff), when pul led high, turns off the power f ets and the cell balance fets, regardless of any other condition.
isl94202 16. higher voltage microcontrollers fn8889 rev.2.00 page 62 of 89 mar 8, 2017 16. higher voltage microcontrollers when using a microcontroller powered by 3.3v or 5v, the design can include pull-up resistors to the microcontroller supply on the communication link and the open-drain sd and eoc pins (instead of pull-up resistors to rgo.) the int pin is a cmos output with a maximum voltage of rgo+0.5v. it is ok to connect this directly to a microcontroller as long as the microcontroller pin does not have a pull up to the 3.3/5v supply. if it does, then a series resistor is recommende d. the fetsoff input on the isl9420 2 is also limited to rgo+0.5v. this is limited by an input esd structure that clamps the voltage. the connection from the c to this pin should include a series resistor to limit any c urrent resulting from the clamp . an example of this connection is shown in figure 16.30 . isl94202 scl sdai sdao controller scl sda 3.3/5v figure 16.30 connection of higher voltage microcontroller sd eoc in_sd in_eoc int in_int * * resistor needed only if c has a pull-up on the in_int pin fetsoff out_fetsoff 10k
isl94202 17. packs with fewer than eight cells fn8889 rev.2.00 page 63 of 89 mar 8, 2017 17. packs with fewer than eight cells see pack configuration on page 27 for help when using fewer than eight cells. this section prese nts options for minimum number of components. however, wh en using the isl94202eval1z ev aluation board with fewer tha n eight cells, it is not necessary to remove components from the pcb. simply tie the unu sed connections together, as shown in figure 17.31 . this normally requires only a different cable. 6 cells 3 cells 4 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss 8 cells cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 5 cells 7 cells vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 vc7 vc6 vc5 vc4 vc3 vc2 vc1 vss cb7 cb6 cb5 cb4 cb3 cb2 cb1 vc8 cb8 vc0 figure 17.31 battery connection options using the isl94202eval1z board
isl94202 18. pc board layout fn8889 rev.2.00 page 64 of 89 mar 8, 2017 18. pc board layout the ac performan ce of this circuit depends greatly on the care taken in designing the pc board. the following are recommendations to achieve optim um high performance from your p c board. ? the use of low inductance compone nts, such as chip resistors a nd chip capacitors, is s trongly recommended. ? minimize signal trace lengths. t his is especially true for the cs1, cs2, and vc0-vc8 in puts. trace inductance and capacitance can easily affect circuit performance. vias in the signal lines add inductance at high frequency and should be avoi ded. ? match channel-to-channel analog i/o trace lengths and layout s ymmetry. this is especially true for the cs1 and cs2 lines, since their inputs are no rmally very low voltage. ? maximize use of ac decoupled pcb layers. all signal i/o lines should be routed over continuous ground planes (i.e., no split planes or ground plane gaps under these lines). avoid vias in t he signal i/o lin es. ? vdd bypass and charge pump capacitors should use wide temperat ure and high frequency diel ectric (x7r or better) with capacitors rated at 2x the maximum operating voltage . ? the charge pump and vdd bypass capacitors should be located cl ose to the isl94202 pins and vdd should have a good ground connection. ? when testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. ? an example pcb layout is shown in figure 18.32 . this figure shows placement of the vdd bypass capacitor close to the vdd pin and with a good ground connection. the charge pump capa citors are also close to the ic. the current-sense lines are shielded by ground plane as much as possible. the ground plane under the ic is shown as an island. the intent of this layout was to minimize voltages induced by emi on the ground plane in the vicinity of the ic. this example assumes a 4-layer board with most signals on the inner layers. vdd cap charge pump gnd plane island ground pink = top blue = bottom current-sense figure 18.32 example 4-layer pcb layout for vdd bypass, charge p ump, and current sense 2 inputs caps
isl94202 18. pc board layout fn8889 rev.2.00 page 65 of 89 mar 8, 2017 18.1 qfn package the qfn package requires additional pcb layout rules for the th ermal pad. the thermal pad i s electrically c onnected to vss supply through the high-resis tance ic substrate. the therma l pad provides heat sinking for the ic. in normal operation, the device should generate little heat, so thermal pad design a nd layout are not too important . however, if the design uses the rgo pin to supply power to external components, then the ic can experience some interna l power dissipation. in this case, careful layout of the therm al pad and the use of thermal vias to direct the heat away from the ic is an important consideration. besides heat dissipation, the thermal pad also p rovides noise reduction by providing a ground plane under the ic. 18.2 circuit diagrams the block diagram on page 3 shows a simple application diagra m with eight cells in series and two cells in parallel (8s2p).
isl94202 19. eeprom fn8889 rev.2.00 page 66 of 89 mar 8, 2017 19. eeprom the isl94202 contains an eeprom array for storing the device co nfiguration parameters, the device calibration values, and some user available registers. access to the eeprom is through the i 2 c port of the device. memory is organized in a memory map as described in: ? registers: summary (eeprom) on page 74 ? registers: summary (ram) on page 75 ? registers: detailed (eeprom) on page 76 ? registers: detailed (ram) on page 82 . when the device powers up, the i sl94202 transfers the contents of the configuration eeprom me mory areas to ram. (note that the user eeprom has no associated ram). an external microc ontroller can read the contents of the configuration ram or the contents of the eeprom. p rior to reading the eeprom, set the eeen bit to 1. this enables access to the eeprom area. if eeen is 0, then a r ead or write occurs in the shadow ram area. the content of t he shadow ram determines t he operation of the d evice. reading from the ram or eeprom can be done using a byte or page read. see: ? current address read on page 70 ? random read on page 70 ? sequent ial read on page 71 ? eepro m access on page 72 ? regis ter protection on page 73 writing to the configuration or u ser eeprom must use a page wri te operation. each page is fou r bytes in length and pages begin at address 0. see: ? page write on page 69 ? register protection on page 73 the eeprom contains an error detection and correction mechanism . when reading a value from the eeprom, the device checks the data value for an error. if there are no errors, then the eeprom value is valid and the ecc_used and ecc_fail bits are set to 0. if there is a 1-bit error, the isl94202 corrects the error and sets the ecc_used bi t. this is a valid operation and value read from the eeprom is correct. during an eeprom read, if there is an error consist ing of two or more bits, the is l94202 sets the ecc_fail bit (ecc_used = 0). this read contains invalid data. the error correction is also act ive during the initial power-on recall of the eeprom values to the shadow ram. the circuit corrects for any one-bit errors. two-bit errors are not correct ed and the contents of the shad ow ram maintain the previous value. internally, the power-on recall circuit uses the ecc_used and e cc_fail bits to deter mine there is a proper recall before allowing the device operation to start. however, an external c cannot use these bits to detect the validity of the shadow ram on power-up or determine the use of the error co rrection mechan ism, because the bits automatically reset on the next valid rea d.
isl94202 20. serial interface fn8889 rev.2.00 page 67 of 89 mar 8, 2017 20. serial interface ? the isl94202 uses a standard i 2 c interface, except the design separates the sda input and output (sdai and sdao) ? separate sdai and sdao lines can be tied together and operate as a typical i 2 c bus ? interface speed is 400khz, maximum 20.1 serial interface conventions the device supports a bidirectiona l bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving de vice as the receiver. the devic e controlling the tran sfer is called the ma ster and the device being controlled is called the sl ave. the master always initiates data transfers and provides th e clock for both transmit and receive operations. therefore, t he isl94202 devices operate as slaves in all applications. when sending or receiving data, the convention with the most si gnificant bit (msb) is sent first. therefore, the first address bit sent is bit 7. 20.2 clock and data data states on the sda line can change only while scl is low. s da state changes during sc l high are reserved for indicating start and stop conditions (see figure 20.33 ). 20.3 start condition all commands are preceded by the start condition, which is a hi gh-to-low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the star t condition and will not respond to any command until this condition has been met (see figure 20.34 ). 20.4 stop condition all communications must be terminated by a stop condition, whic h is a low-to-high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode afte r a read sequence. a stop condition is only issued after t he transmitting device has rele ased the bus (see figure 20.34 ).
isl94202 20. serial interface fn8889 rev.2.00 page 68 of 89 mar 8, 2017 20.5 acknowledge acknowledge is a software conven tion used to indicate successfu l data transfer. the transmitting device, either master or slave, releases the bus after transmitting eight bits. during t he ninth clock cycle, the receiver pulls the sda line low to acknowledge that it received the eight bits of data (see figure 20.35 ). the device responds with an acknowledge after recognition of a start condition and the correct slave byte. if a write operation is selected, the device responds with an acknowledge after the receipt of each subsequent eight bits. the device acknowledges all incoming data and address bytes, except for th e slave byte when th e contents do not m atch the devices internal slave address. in the read mode, the device tran smits eight bits of data, rele ases the sda line, then monitors the line for an acknowledge. if an acknowledge is detected a nd no stop condition is generate d by the master, the device wi ll continue to transmit data. the device terminates further d ata transmissions if an acknowle dge is not detected. the master must then issue a stop condition to return the device to standby mode and place the de vice into a known state. scl sda data stable data change data stable figure 20.33 valid data changes on i 2 c bus scl sda start stop figure 20.34 i 2 c start and stop bits 8 1 9 data output from transmitter data output from receiver start acknowledge figure 20.35 acknowledge response from receiver scl from master
isl94202 20. serial interface fn8889 rev.2.00 page 69 of 89 mar 8, 2017 20.6 write operations 20.6.1 byte write for a byte write operation, the d evice requires the slave addre ss byte and a word address by te. this gives the master access to any one of th e words in the array . after receipt of the word address byte, the device responds with an acknowledge and awaits the next eight bits of data. after recei ving the eight bits of the data byte, the device again responds with an acknowledge. the master th en terminates th e transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, s o the device will not respond to any requests from the master. th e sda output is at high impedance. see figure 20.36 . a write to a protected block of memory suppresses the acknowled ge bit. when writing to the eeprom, write to all addresse s of a page wi thout an intermediate read operation or use a page write command. each page is four bytes long, starting at addres s 0. 20.6.2 page write a page write operation is initiate d in the same ma nner as the b yte write operation; but inst ead of termina ting the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the dev ice will respond with an acknowledge and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of t he page, it rolls over and goes back to 0 on the same page. this means that the maste r can write four bytes to the pa ge starting at any location on that page. if the master begins writing at location 2 and loads four bytes , then the fir st two bytes are written to locations 2 and 3 and the last two bytes are written to locatio ns 0 and 1. afterwards, the add ress counter would point to l ocation 2 of the page that was just written. if the master supplies more than four bytes o f data, then new data overwrites the previous data, one byte at a time. see figure 20.37 . do not write to addresses 58h t hrough 7fh or locations higher t han address abh, since these addresses access registers that are reserved. writing to these locations can result in unexpected device operation. 0 0101 00 0 s t a r t s t o p slave byte byte address data a c k a c k a c k sda bus signals from the slave signals from the master figure 20.36 byte write sequence isl94202: slave byte = 50h (addr = 0) watchdog timer reset isl94202: slave byte = 52h (addr = 1) figure 20.37 writing 4 bytes to a 4-byte page starting at locati on 2 address pointer star ts and ends here address = 0 data byte 3 address = 1 data byte 4 address = 2 data byte 1 address = 3 data byte 2
isl94202 20. serial interface fn8889 rev.2.00 page 70 of 89 mar 8, 2017 20.7 read operations read operations are initiated in the same manner as write opera tions with the exception that the r/w bit of the slave address byte is set to one. ther e are three basi c read operatio ns: current address reads, r andom reads, and sequential reads. 20.7.1 current address read internally the device contains an address counter that maintain s the address of the last word read incremented by one. therefore, if the last read was to address n, the next read ope ration would access data from address n+1. on power-up, the address of the address counter is undefined, requiring a re ad or write operation for initialization. see figure 20.39 on page 71 . upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then tran smits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. it should be noted that the ninth clock cycle of the read opera tion is not a dont care. to terminate a read operation, the master must either issue a stop condition during the ninth cycl e or hold sda high during the ninth clock cycle and then issue a stop condition. 20.7.2 random read random read operation allows the master to access any memory lo cation in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a dummy write operation. the maste r issues the start condition and the slav e address byte, receive s an acknowledge, then issues the word address bytes. after acknowledging receipts of the wor d address bytes, the master im mediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the de vice and then by the eight bit word. the master terminates the read operation by not respondin g with an acknowledge and then issuing a stop condition (see figure 20.40 ) 20.7.3 sequential read sequential reads can be initiated as either a current address r ead or random address read . the first data byte is transmitted as with the other mo des, however, th e master now re sponds with an acknowledge, indicating it requires additional data. the device cont inues to output data for each a cknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuin g a stop condition the data output is sequential, wit h the data from address n fol lowed by the data from address n+1. the address counter for read operations increments th rough all page a nd column addr esses, allowing the entire memory contents to be serially read during one operati on. at the end of the address s pace the counter rolls over to address 0000h and the device continues to output data f or each acknowledge received. see figure 20.41 for the acknowledge and data transfer sequence. 0 0101 00 0 s t a r t s t o p slave byte register address data(1) a c k a c k a c k sda bus signals from the slave signals from the master figure 20.38 page write sequence data(n) a c k watchdog timer isl94202: slave byte = 50h (addr = 0) isl94202: slave byte = 52h (addr = 1)
isl94202 20. serial interface fn8889 rev.2.00 page 71 of 89 mar 8, 2017 20.7.4 eeprom access the user is advised not to use p age transfers when reading or w riting to eeprom. only single byte i 2 c transactions should be used. in addition, write transactions should be sep arated with a 30ms delay to enable each byte write operation to complete. 20.7.5 eeprom read the isl94202 has a special requirement when reading the eeprom. an eeprom read operation from the first byte of a four byte page (locations 0h, 4h, 8h, etc.) initiates a recal l of the eeprom page. this r ecall takes more than 200s, figure 20.39 current address read sequence figure 20.40 random read sequence figure 20.41 sequential read sequence 1 0101 00 0 s t a r t s t o p slave byte data a c k n a c k a c k sda bus signals from the slave signals from the master isl94202: slave byte = 50h (addr = 0) isl94202: slave byte = 52h (addr = 1) watchdog timer reset s t a r t s t o p slave byte data a c k n a c k s t a r t slave byte register address a c k a c k sda bus signals from the slave signals from the master a c k watchdog timer reset isl94202: slave byte = 50h (addr = 0) isl94202: slave byte = 52h (addr = 1) 0 0101 00 01 0101 00 0 s t a r t s t o p slave byte data a c k n a c k s t a r t slave byte register address a c k a c k sda bus signals from the slave signals from the master a c k watchdog timer reset isl94202: slave byte = 50h (addr = 0) isl94202: slave byte = 52h (addr = 1) 0 0101 00 01 0101 00 0
isl94202 20. serial interface fn8889 rev.2.00 page 72 of 89 mar 8, 2017 so the first byte may not be r eady in time for a standard i 2 c response. it is necessary to read this first byte of every page two times. 20.7.6 eeprom write the isl94202 also has a special requirement when writing the ee prom. an eeprom write operation to the first byte of a four byte page (locations 0 h, 4h, 8h, etc.) initiates a re call of the eeprom page. this recall takes more than 200s, so the first byte may not b e ready in time for a standar d i 2 c response. it is necessary to write this first byte of every page two times. these dup licate writes should be separa ted with a 30ms delay and followed with a 30ms delay. again, only single byte transactions should be used with a 30ms delay between each write operation. 20.8 synchronizing microcontroller operations with internal scan internal scans occur every 32ms i n normal mode, 256ms in idle m ode and 512ms in doze mode. the internal scan normally takes about 1.3ms, with every fourth scan taking about 1.7ms. while the percentage of time taken by the scan is small, it is long enough that random communications from the microcontroller can coincide w ith the interna l scan. when the two scans happen at the same time, errors can occur in the recorded values. to avoid errors in the recorded values, the goal is to synchron ize external i 2 c transactions so that they only occur during the devices low power state (see figure 10.22 on page 43 .) to assist in the synchronizat ion, the microcontroller can us e the int_scan bit. this bit is 0 during the internal scan and 1 during the low power state. the microcontroller software sh ould look for the int_scan bit t o go from a 0 to a 1 to allow the maximum time to complete read or write operations . this insures that the result s reported to the c are from a single scan and changes made do not interfere with state m achine detection and timing.
isl94202 21. register protection fn8889 rev.2.00 page 73 of 89 mar 8, 2017 21. register protection the entire eeprom memory is write protected on initial power-up and during normal operation. an enable byte allows writing to various areas of the memory array. the enable byte is encoded, so that a value of 0 in the eepro m enable register (89h) enables access to the shadow memory (ram), a value of 1 allows access to the eeprom. after a read or write of the eeprom, the microcontroller should reset the eeprom enable register value back to zero to prevent inadvertent writes to the eeprom and to turn of f the eeprom block to reduce current consumption. if the microcontroller fails to re set the eeprom bit and commun ications to the chip stops, then the watchdog timer will reset the eeprom select bit.
isl94202 22. register s: summary (eeprom) fn8889 rev.2.00 page 74 of 89 mar 8, 2017 22. registers: summary (eeprom) table 22.13 eeprom register summary eeprom (configured as 32 4-byte pages) page addr 0x 1x 2x 3x 4x 5x 0 0 overvoltage level overvoltage delay timer minimum cb delta charge over-temperature level internal over-temperature level user eeprom 1 2 overvoltage recovery undervoltage delay timer maximum cb delta charge over-temp recovery internal over-temperature recovery 3 1 4 undervoltage level open wire timing cell balance on time charge under-temperature level sleep voltage 5 6 undervoltage recovery discharge overcurrent timeout settings, discharge setting cell balance off time charge under-temperature recovery sleep delay timer/ watchdog timer 7 2 8 ovlo threshold charge overcurrent timeout settings, charge overcurrent setting minimum cb temperature level discharge over-temperature level sleep mode timer reserved 9 cells config a uvlo threshold short-circuit timeout settings/ recovery settings, short-circuit setting minimum cb temperature recovery discharge over-temperature recovery features 1 b features 2 3 c eoc voltage level minimum cb volts maximum cb temperature level discharge under-temperature level reserved d e low voltage charge level maximum cb volts maximum cb temperature recovery discharge under-temperature recovery f
isl94202 23. registers: summary (ram) fn8889 rev.2.00 page 75 of 89 mar 8, 2017 23. registers: summary (ram) table 23.14 ram register summary ram page addr 8x 9x ax 0 0 status1 cell1 voltage it voltage 1 status2 2 status3 cell2 voltage xt1 voltage 3 status4 1 4 cell balance cell3 voltage xt2 voltage 5 analog out 6 fet cntl/override control bits cell4 voltage vbatt/16 voltage 7 override control bits 2 8 force ops cell5 voltage vrgo/2 voltage 9 ee write enable a cellmin voltage cell6 voltage 14-bit adc voltage b 3 c cellmax voltage cell7 voltage reserved d e isense voltage cell8 voltage f
isl94202 24. register s: detailed (eeprom) fn8889 rev.2.00 page 76 of 89 mar 8, 2017 24. registers: detailed (eeprom) table 24.15 eeprom register detail bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210 00 01 overvoltage threshold if any cell voltage is above this threshold voltage for an over voltage delay time, the charge fet is turned off. default (hex): 1e2a (v): 4.25 charge detect pulse width these bits set the duration of the charger monitor pulse width. ovlb ovla ovl9 ovl8 ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 cpw3 cpw2 cpw1 cpw0 0000 = 0ms to 1111 = 15ms; default = 1ms 02 03 overvoltage recovery if all cells fall below this overvoltage recovery level, the ch arge fet is turned on. default (hex): 0dd4 (v): 4.15 reserved ovrb ovra ovr9 ovr8 ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 04 05 undervoltage threshold if any cell voltage is below this threshold voltage for an unde rvoltage delay time, the discharge fet is turned off. default (hex): 18ff (v): 2.7 load detect pulse width these bits set the duration of the charger monitor pulse width. uvlb uvla uvl9 uvl8 uvl7 uvl6 uvl5 uvl4 uvl3 uvl2 uvl1 uvl0 lpw3 lpw2 lpw1 lpw0 0000 = 0 ms to 1111 = 15ms; default = 1ms 06 07 undervoltage recovery if all cells rise above this overvoltage recovery level (and th ere is no load), the discharge fet is turned on. default (hex): 09ff (v): 3.0 reserved uvrb uvra uvr9 uvr8 uvr7 uvr6 uvr5 uvr4 uvr3 uvr2 uvr1 uvr0 08 09 overvoltage lockout threshold if any cell voltage is above thi s threshold for five successive scans, then the device is in an overvoltage lockout condition. in this condition, the charge fet is turned off, the cell balance fets are turned off, the ovlo bit is set, and the psd o utput is set to active. default (hex): 0e7f (v): 4.35 reserved ovlo b ovlo a ovlo 9 ovlo 8 ovlo 7 ovlo 6 ovlo 5 ovlo 4 ovlo 3 ovlo 2 ovlo 1 ovlo 0 0a 0b undervoltage lockout threshold if any cell voltage is below this threshold for five successive scans, then the device is in an undervoltage lockout condition. in this condition, the disch arge fet is turned off and the uvlo bit is set. the device also powers down (unless overri dden). default (hex): 0600 (v): 1.8 reserved uvlo b uvlo a uvlo 9 uvlo 8 uvlo 7 uvlo 6 uvlo 5 uvlo 4 uvlo 3 uvlo 2 uvlo 1 uvlo 0 0c 0d end-of-charge (eoc) threshold if any cell exceeds this level, th en the eoc output and the eoc bit are set. default (hex): 0dff (v): 4.2 reserved eocb eoca eoc9 eoc8 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0 0e 0f low voltage charge level if the voltage on any cell is less than this level, then the pc fet output turns on instead of the pc output. to disable this function, set the value to ze ro or set the pcfete bit to 0. default (hex): 07aa (v): 2.3 reserved lvch b lvch a lvch9 lvch8 lvch7 lvch6 lvch5 lvch4 lvch3 lvch2 lvch1 lvch0 10 11 overvoltage delay time out this value sets the time that i s required for any cell to be ab ove the overvoltage threshold before an overvoltage condition is detected. default (hex): 0801 (s): 1 reserved ovdt b ovdt a ovdt 9 ovdt 8 ovdt 7 ovdt 6 ovdt 5 ovdt 4 ovdt 3 ovdt 2 ovdt 1 ovdt 0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 threshold hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - = threshold hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - =
isl94202 24. register s: detailed (eeprom) fn8889 rev.2.00 page 77 of 89 mar 8, 2017 12 13 undervoltage delay time out this value sets the time that i s required for any cell to be be low the undervoltage threshold before an undervoltage condition is detected. default (hex): 0801 (s): 1 reserved uvdt b uvdt a uvdt 9 uvdt 8 uvdt 7 uvdt 6 uvdt 5 uvdt 4 uvdt 3 uvdt 2 uvdt 1 uvdt 0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 14 15 open-wire timing (owt) this value sets the width of the open-wire test pulse for each cell input. default (hex): 0214 (ms): 20 reserved owt 9 owt 8 owt 7 owt 6 owt 5 owt 4 owt 3 owt 2 owt 1 owt 0 0 = s 1 = ms 0 to 512 16 17 discharge overcurrent time out/threshold time out a discharge overcurrent needs to remain for this time period pr ior to entering a discharge overcurrent condition . this is a 12-bi t value: lower 10 bits set the time. upper bits set the time base. default (hex): 44a0 (ms): (mv): 160 32 threshold this value sets the voltage across current-sense resistor that creates a discharge overcurrent condition. ocd2 ocd1 ocd0 ocdt b ocdt a ocdt 9 ocdt 8 ocdt 7 ocdt 6 ocdt 5 ocdt 4 ocdt 3 ocdt 2 ocdt 1 ocdt 0 000 = 4mv 001 = 8mv 010 = 16mv 011 = 24mv 100 = 32mv 101 = 48mv 110 = 64mv 111 = 96mv 00 = s 01 = ms 10 = s 11 = min 0 to 1024 18 19 charge overcurrent time out/threshold time out a charge overcurrent needs to remain for this time period prior to entering a charge overcurrent condition. this is a 12-bit value: lower 10 bits se t the time. upper bits set the time base. default (hex): 44a0 (ms): (mv): 160 8 threshold this value sets the voltage across current-sense resistor that creates a charge overcurrent condition occ2 occ1 occ0 occt b occt a occt 9 occt 8 occt 7 occt 6 occt 5 occt 4 occt 3 occt 2 occt 1 occt 0 000 = 1mv 001 = 2mv 010 = 4mv 011 = 6mv 100 = 8mv 101 = 12mv 110 = 16mv 111 = 24mv 00 = s 01 = ms 10 = s 11 = min 0 to 1024 1a 1b discharge short-circuit time out/threshold time out a short-circuit current needs to remain for this time period pr ior to entering a short- circuit condition. thi s is a 12 bit value: lower 10 bits set the time. upper bits set the time base default (hex): 60c8 (s): (mv): 200 128 threshold this value sets the voltage across current-sense resistor that creates a short-circuit condition scd2 scd1 scd0 sctb scta sct9 sct8 sct7 sct6 sct5 sct4 sct3 sct2 sct1 sct0 000 = 16mv 001 = 24mv 010 = 32mv 011 = 48mv 100 = 64mv 101 = 96mv 110 = 128mv 111 = 256mv 00 = s 01 = ms 10 = s 11 = min 0 to 1024 table 24.15 eeprom regis ter detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210
isl94202 24. register s: detailed (eeprom) fn8889 rev.2.00 page 78 of 89 mar 8, 2017 1c 1d cell balance minimum voltage (cbmin) if all cell voltages are less th an this voltage, then cell bala nce stops. default (hex): 0a55 (v): 3.1 reserved cbvl b cbvl a cbvl9 cbvl8 cbvl7 cbvl6 cbvl5 cbvl4 cbvl3 cbvl2 cbvl1 cbvl0 1e 1f cell balance maximum voltage (cbmax) if all cell voltages are great er than this voltage, then cell b alance stops. default (hex): 0d70 (v): 4.0 reserved cbvu b cbvu a cbvu 9 cbvu 8 cbvu 7 cbvu 6 cbvu 5 cbvu 4 cbvu 3 cbvu 2 cbvu 1 cbvu 0 20 21 cell balance minimum differential voltage (cbmindv) if the difference between the voltage on celln and the lowest v oltage cell is less than this voltage, then cell balance for celln stops. default (hex): 0010 (mv): 20 reserved cbdl b cbdl a cbdl 9 cbdl 8 cbdl 7 cbdl 6 cbdl 5 cbdl 4 cbdl 3 cbdl 2 cbdl 1 cbdl 0 22 23 cell balance maximum diffe rential voltage (cbmaxdv) if the difference between the voltage on celln and the lowest v oltage cell is greater than this voltage, then cell bal ance for celln stops and the ce llf flag is set. default (hex): 01ab (mv): 500 reserved cbdu b cbdu a cbdu 9 cbdu 8 cbdu 7 cbdu 6 cbdu 5 cbdu 4 cbdu 3 cbdu 2 cbdu 1 cbdu 0 24 25 cell balance on time (cbon) cell balance is on for this set amount of time, unless another condition indicates that there should be no cell balance. this is a 12-bit value: lower 10 bits set the time. upper 2 bits set the time base. default (hex): 0802 (s): 2 reserved cbon tb cbon ta cbon t9 cbon t8 cbon t7 cbon t6 cbon t5 cbon t 4 cbon t3 cbon t2 cbon t1 cbon t0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 26 27 cell balance off time (cboff) cell balance is off for the set amount of time. this is a 12-bi t value: lower 10 bits set the time. upper 2 bits set the time base. default (hex): 0802 (s): 2 reserved cbof tb cbof ta cbof t9 cbof t8 cbof t7 cbof t6 cbof t5 cbof t4 cbof t3 cbof t2 cbof t1 cbof t0 00 = s 01 = ms 10 = s 11 = min 0 to 1024 28 29 cell balance minimum temperature limit (cbuts) if the external temperature 1 or the external temperature 2 (xt 2m = 0) is greater than this voltage, then cell balance stops. the voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 0bf2 (v): (c): 1.344 -10 reserved cbut sb cbut sa cbut s9 cbut s8 cbut s7 cbut s6 cbut s5 cbut s4 cbut s3 cbut s2 cbut s1 cbut s0 2a 2b cell balance minimum tempera ture recovery level (cbutr) if the external temperature 1 and the external temperature 2 (x t2m = 0) all recover and fall below this voltage, then cell balance can resume (all other conditions ok). the voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 0a93 (v): (c): 1.19 +5 reserved cbut rb cbut ra cbut r9 cbut r8 cbut r7 cbut r6 cbut r5 cbut r4 cbut r3 cbut r2 cbut r1 cbut r0 2c 2d cell balance maximum temperature limit (cbots) if the external temperature 1 or the external temperature 2 (xt 2m = 0) is less than this voltage, then cell balance stops. the voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 04b6 (v): (c): 0.530 +55 reserved cbot sb cbot sa cbot s9 cbot s8 cbot s7 cbot s6 cbot s5 cbot s4 cbot s3 cbot s2 cbot s1 cbot s0 2e 2f cell balance maximum tempera ture recovery level (cbotr) if the external temperature 1 and the external temperature 2 te mperature (xt2m = 0) all recover and rise above this voltage, then cell balance can resume (all other conditions ok). the voltage is based on recommended external co mponents (see figure 10.26 on page 50 ). default (hex): 053e (v): (c): 0.590 +50 reserved cbot rb cbot ra cbot r9 cbot r8 cbot r7 cbot r6 cbot r5 cbot r4 cbot r3 cbot r2 cbot r1 cbot r0 for all temperature limits, tgain bit = 0, temperature gain = 2 table 24.15 eeprom regis ter detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210
isl94202 24. register s: detailed (eeprom) fn8889 rev.2.00 page 79 of 89 mar 8, 2017 30 31 charge over-temperature voltage if external temperature 1 or the external temperature 2 is less than this voltage, then the charge fet is turned off a nd the cot bit is set. the voltag e is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 04b6 (v): (c): 0.530 +55 reserved cots b cots a cots 9 cots 8 cots 7 cots 6 cots 5 cots 4 cots 3 cots 2 cots 1 cots 0 32 33 charge over-temperature recovery voltage if external temperature 1 or the external temperature 2 rise ab ove this setting, then the charge fet is turned on and the cot bit is reset (unless ov errides are in place). the voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 053e (v): (c): 0.590 +50 reserved cotr b cotr a cotr 9 cotr 8 cotr 7 cotr 6 cotr 5 cotr 4 cotr 3 cotr 2 cotr 1 cotr 0 34 35 charge under-temperature voltage if external temperature 1 or the external temperature 2 is grea ter than this voltage, then the charge fet is turned o ff and the cut bit is set. the v oltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 0bf2 (v): (c): 1.344 -10 reserved cuts b cuts a cuts 9 cuts 8 cuts 7 cuts 6 cuts 5 cuts 4 cuts 3 cuts 2 cuts 1 cuts 0 36 37 charge under-temperature recovery voltage if external temperature 1 or the external temperature 2 fall be low this setting, then the charge fet is turned on and the cut bit is reset (unless overri des are in place). the voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 0a93 (v): (c): 1.190 +5 reserved cutr b cutr a cutr 9 cutr 8 cutr 7 cutr 6 cutr 5 cutr 4 cutr 3 cutr 2 cutr 1 cutr 0 38 39 discharge over-temperature voltage if external temperature 1 or the external temperature 2 is less than this voltage, then the discharge fet is turned off and the dot bit is set. the vol tage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 4b6 (v): (c): 0.530 +55 reserved dots b dots a dots 9 dots 8 dots 7 dots 6 dots 5 dots 4 dots 3 dots 2 dots 1 dots 0 3a 3b discharge over-temperature recovery voltage if external temperature 1 or the external temperature 2 rise ab ove this setting, then the discharge fet is turned on and the dot bit is reset (unless overrides are in place). the voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 053e (v): (c): 0.590 +50 reserved dotr b dotr a dotr 9 dotr 8 dotr 7 dotr 6 dotr 5 dotr 4 dotr 3 dotr 2 dotr 1 dotr 0 3c 3d discharge under-temperature voltage if external temperature 1 or the external temperature 2 is grea ter than this voltage, then the discharge fet is turned off and the dut bit is set. th e voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 0bf2 (v): (c): 1.344 -10 reserved duts b duts a duts 9 duts 8 duts 7 duts 6 duts 5 duts 4 duts 3 duts 2 duts 1 duts 0 3e 3f discharge under-temperature recovery voltage if external temperature 1 or the external temperature 2 fall be low this setting, then the discharge fet is turned on and the dut bit is reset (unless ove rrides are in place). the voltage is based on recommended external components (see figure 10.26 on page 50 ). default (hex): 0a93 (v): (c): 1.190 +5 reserved dutr b dutr a dutr 9 dutr 8 dutr 7 dutr 6 dutr 5 dutr 4 dutr 3 dutr 2 dutr 1 dutr 0 40 41 internal over-temperature voltage if the internal temperature is greater than this voltage, then all fets are turned off and the iot bit is set. default (hex): 67ch (v): (c): 0.73 +115 reserved iots b iots a iots 9 iots 8 iots 7 iots 6 iots 5 iots 4 iots 3 iots 2 iots 1 iots 0 42 43 internal over-temperature recovery voltage when the internal temperature voltage drops below this level, then the fets can be turned on again and the iot bit is reset on the next c read. default (hex): 621h (v): (c): 0.69 +95 reserved iotr b iotr a iotr 9 iotr 8 iotr 7 iotr 6 iotr 5 iotr 4 iotr 3 iotr 2 iotr 1 iotr 0 44 45 sleep level voltage if any cell voltage is below this threshold voltage for a sleep delay time, the device goes into the sleep mode. default (hex): 06aa (v): 2.0 reserved sllb slla sll 9 sll 8 sll 7 sll 6 sll 5 sll 4 sll 3 sll 2 sll 1 sll 0 table 24.15 eeprom regis ter detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210
isl94202 24. register s: detailed (eeprom) fn8889 rev.2.00 page 80 of 89 mar 8, 2017 46 47 sleep delay timer/watchdog timer sleep delay this value sets the time that i s required for any cell to be be low the sleep voltage threshold before the device enters the sleep mode. lower 10 bits set the time. upper 1 bit sets the time base. default (hex): fc0f sleep wdt (s) (s) 1 31 watchdog timer (wdt) time allowed the microcontroller between i 2 c slave byte writes to the isl94202 after setting any override bit. wdt4 wdt3 wdt2 wdt1 wdt0 slta slt9 slt8 slt7 slt6 slt5 slt4 slt3 slt2 slt1 slt0 0 to 31 seconds 00 = s 01 = ms 10 = s 11 = min 0 to 511 48 49 sleep mode timer/cell configuration mode timer time required to enter sleep mode from the doze mode when no cu rrent is detected. default (hex): 83ff idle/ doze: sleep mode (min) (min) cells 15 240 3 cell configuration only these combinations are acceptable. any other combination w ill prevent any fet from turning on. cell8 cell7 cell6 cell5 cell4 cell3 cell2 cell1 mod7 mod6 mod5 mod4 mod3 mod2 mod1 mod0 8 7 6 5 4 3 2 1 number of cells idle and doze mode: [mod3:0] = 0 to 15 minutes sleep mode [mod7:4] = 0 to 240 minutes example: value = 0101 1010 idle/doze = 10 minutes sleep = 80 minutes 1 0 0 0 0 0 1 1 3 cells connected 1 1 0 0 0 0 1 1 4 cells connected 1 1 0 0 0 1 1 1 5 cells connected 1 1 1 0 0 1 1 1 6 cells connected 1 1 1 0 1 1 1 1 7 cells connected 1 1 1 1 1 1 1 1 8 cells connected table 24.15 eeprom regis ter detail (continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210
isl94202 24. register s: detailed (eeprom) fn8889 rev.2.00 page 81 of 89 mar 8, 2017 table 24.16 eeprom register detail (feature controls) bit/ addr 76543210 4a cfpsd cellf psd 1 = activates psd output when a cell fail condition occurs. 0 = does not activate psd output when a cell fails condition occurs. reserved xt2m xtemp 2 mode control 1 = xt2 monitors fet temp. cell balance outputs are not shut off when xt2 temperature exceeds cell balance limits 0 = xt2 monitors cell temp. (normal operation.) tgain external temp gain 1 = gain of it, xt1 and xt2 inputs is 1x. 0 = gain of it, xt1 and xt2 inputs is 2x. reserved, this bit must be 0. pcfete precharge fet enable 1 = precharge fet output turns on instead of the cfet output when any of the cell voltages are below the under the lvchg threshold. 0 = precharge fet is not used dowd disable open-wire scan 1 = disable the input open- wire detection scan 0 = enable the input open- wire detection scan owpsd open-wire psd 1 = responds automatically to the input open wire condition and sets psd. 0 = responds automatically to the input open wire condition and does not set psd. 4b cbdd cb during discharge 1 = do balance during discharge 0 = no balance during discharge when both cbdd and cbdc equal 0, cell balance is turned off. cbdc cb during charge 1 = do balance during charge 0 = no balance during charge when both cbdd and cbdc equal 0, cell balance is turned off. dfoduv dfet on during uv (charging) 1 = keep dfet on while the pack is charging, regardless of the cell voltage. this minimizes dfet power dissipation during uv, when the pack is charging 0 = normal dfet operation. cfodov cfet on during ov (discharging) 1 = keep cfet on while the pack is discharging, regardless of the cell voltage. this minimizes cfet power dissipation during ov, when the pack is discharging 0 = normal cfet operation. uvlopd enable uvlo power-down 1 = the device powers down when detecting an uvlo condition. 0 = when a uvlo condition is detected, the device remains powered. reserved reserved cb_eoc enable cbal during eoc 1 = cell balance occurs during eoc condition regardless of current direction. 0 = cell balance turns off during eoc if there is no current flowing. 4c 4f reserved 50 57 user eeprom available to the user (note: there is no shadow memory associat ed with these registers).
isl94202 25. registers: detailed (ram) fn8889 rev.2.00 page 82 of 89 mar 8, 2017 25. registers: detailed (ram) table 25.17 ram register detail (status and control) bit/ addr 765 4 3 2 1 0 80 (read only) these bits are set and reset by the device. cut charge under-temp an external thermistor shows the temp is lower than the minimum charge temp limit. cot charge over-temp an external thermistor shows the temp is higher than the maximum charge temp limit. dut discharge under-temp an external thermistor shows the temp is lower than the minimum discharge temp limit. dot discharge over-temp an external thermistor shows the temp is higher than the maximum discharge temp limit. uvlo undervoltage lockout at least one cell is below the undervoltage lockout threshold. uv undervoltage at least one cell has an undervoltage condition. ovlo overvoltage lockout at least one cell is above the overvoltage lockout threshold. ov overvoltage at least one cell has an overvoltage condition. 81 (read only) these bits are set and reset by the device eochg end of charge end of charge voltage reached. reserved open open wire an open input circuit is detected. cellf cell fail indicates that there is more than the maximum allowable voltage difference between cells. dsc discharge short-circuit short-circuit current detected. doc discharge overcurrent excessive discharge current detected. coc charge overcurrent excessive charge current detected. iot internal over-temp the internal sensor indicates an over-temp condition. 82 (read only) these bits are set and reset by the device lvchg low voltage charge at least one cell voltage < lvchg threshold. if set, pcfet turns on instead of cfet. int_scan internal scan in-progress when this bit is 0 for the duration of the internal scan. ecc_fail eeprom error correct fail eeprom error correction failed. two bits failed, error not corrected. previous value retained. ecc_used eeprom error correct eeprom error correction used. one bit failed, bit error corrected. dching discharging indicates that a discharge current is detected. charge current is flowing out of the pack. ching charging indicates that a charge current is detected. charge current is flowing into the pack. ch_prsnt chrgr present set to 1 during coc, while charger is attached. (chmon > threshold.) if clmon = 0, bit resets automatically. if clmon = 1, bit resets by c read of register. ld_prsnt load present set to 1 during doc or dsc, while load attached. (ldmon < threshold.) if ccmon = 0, bit resets automatically. if ccmon = 1, bit resets by c read of register. 83 (read only) these bits are set and reset by the device reserved in_sleep in sleep mode no scans. rgo remains on, vref off. monitors for a charger or load connection. in_doze in doze mode scans every 512ms in_idle in idle mode scans every 256ms cbuv cell balance undervoltage all cell voltages < the minimum allowable cell balance voltage threshold. cbov cell balance overvoltage all cell voltages > the maximum allowable cell balance voltage threshold. cbut cell balance under-temp xt1 or xt2 indicates temp < allowable cell balance low temperature threshold cbot cell balance over-temp xt1 or xt2 indicates temp > allowable cell balance high temperature threshold 84 (r/w ) cell balance fet control bits these bits control the cell balance when the external controlle r overrides the internal cell balance operation. cb8on cb7on cb6on cb5on cb4on cb3on cb2on cb1on if ccbal = 1, cbal_on = 1 and cbnon bit = 1 the cell balance f et is on. if ccbal = 0, cbal_on = 0 or cbnon bit = 0 the cell balance fe t is off.
isl94202 25. registers: detailed (ram) fn8889 rev.2.00 page 83 of 89 mar 8, 2017 85 (r/w ) analog mux control bits voltage monitored by adc when microcontroller overrides the internal scan operation. current gain setting current gain set when current is monitored by adc. only used when microcontroller overrides the internal scan. adc conversion start reserved adcstrt cg1 cg0 ao3 ao2 ao1 ao0 ext c sets this bit to 1 to start a conversion cg1 0 0 0 0 1 1 0 1 1 gain x50 x5 x500 x500 ao3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 off vc1 vc2 vc3 vc4 vc5 vc6 vc7 ao3 2 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 vc8 pack current vbat/16 rgo/2 xt1 xt2 it off 86 (r/w ) clr_lerr clear load error 1 = resets load monitor error condition. this bit is automatically cleared. only active when ccmon = 1 lmon_en load monitor enable 1 = load monitor on 0 = load monitor off only active when clmon = 1 clr_err clear charge error 1 = resets charge monitor error condition. this bit is automatically cleared. only active when ccmon = 1 cmon_en charge monitor enable 1 = charger monitor on 0 = charger monitor off. only active when ccmon = 1 psd pack shut down 1 = psd on 0 = psd off pcfet pre-charge fet 1 = pcfet on 0 = pcfet off bit = 0 if doc or dsc, unless the automatic response is disabled by cfet bit. (4) cfet charge fet 1 = cfet on 0 = cfet off bit = 0 if coc, unless the automatic response is disabled by cfet bit. (4) dfet discharge fet 1 = dfet on 0 = dfet off bit = 0 if doc or dsc unless the automatic response is disabled by cfet bit. (4) 87 (r/w ) reserved cfet c does fet control 1 = fets controlled by external c. 0 = norm automatic fet control (7), (10) ccbal c does cell balance 1 = internal balance disabled. c manages cell balance 0 = internal balance enabled. (7) clmon c does load monitor 1 = load monitor on 0 = load monitor off (7) ccmon c does charger mon 1 = charge monitor on 0 = charge monitor off (7) cscan c does scan 1 = no auto scan. system controlled by c. 0 = normal scan (7), (99) ow_strt open wire start 1 = does one open-wire scan (bit auto reset to 0) 0 = no scan only active if dowd = 1 or cscan = 1 cbal_on cell balance on 1 = (cbnon =1) outputs on 0 = cell bal outputs off only active if ccbal= 1. 88 (r/w ) reserved reserved reserved reserved pdwn power-down 1 = power-down the device. 0 = normal operation sleep set sleep 1 = put device into sleep mode. 0 = normal operation doze set doze 1 = put device into doze mode. 0 = normal operation idle set idle 1 = put device into idle mode0= normal operation. 89 (r/w ) eeprom enable eeen reserved. these bits should be zero. 0 = ram access 1 = eeprom access table 25.17 ram register detail ( status and control) (continued) bit/ addr 765 4 3 2 1 0
isl94202 25. registers: detailed (ram) fn8889 rev.2.00 page 84 of 89 mar 8, 2017 table 25.18 ram register de tail (monitored voltages) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210 8a 8b cell minimum voltage this is the voltage of the cell with the minimum voltage. reserved cellm inb cellm ina cellm in9 cellm in8 cellm in7 cellm in6 cellm in5 cellm in4 cellm in3 cellm in2 cellm in1 cellm in0 8c 8d cell maximum voltage this is the voltage of the cell with the maximum voltage. reserved cellm axb cellm axa cellm ax9 cellm ax8 cellm ax7 cellm ax6 cellm ax5 cellm ax4 cellm ax3 cellm ax2 cellm ax1 cellm ax0 8e 8f pack current this is the current flowing into or out of the pack. polarity identified by ching and dching bits. reserved isnsb isnsa isns9 isns8 isns7 isns6 isns5 isns4 isns3 isns2 isns1 isns0 90 91 cell 1 voltage this is the voltage of cell1. reserved cell1 b cell1 a cell1 9 cell1 8 cell1 7 cell1 6 cell1 5 cell1 4 cell1 3 cell1 2 cell1 1 cell1 0 92 93 cell 2 voltage this is the voltage of cell2. reserved cell2 b cell2 a cell2 9 cell2 8 cell2 7 cell2 6 cell2 5 cell2 4 cell2 3 cell2 2 cell2 1 cell2 0 94 95 cell 3 voltage this is the voltage of cell3. reserved cell3 b cell3 a cell3 9 cell3 8 cell3 7 cell3 6 cell3 5 cell3 4 cell3 3 cell3 2 cell3 1 cell3 0 96 97 cell 4 voltage this is the voltage of cell4. reserved cell4 b cell4 a cell4 9 cell4 8 cell4 7 cell4 6 cell4 5 cell4 4 cell4 3 cell4 2 cell4 1 cell4 0 98 99 cell 5 voltage this is the voltage of cell5. reserved cell5 b cell5 a cell5 9 cell5 8 cell5 7 cell5 6 cell5 5 cell5 4 cell5 3 cell5 2 cell5 1 cell5 0 9a 9b cell 6 voltage this is the voltage of cell6. reserved cell6 b cell6 a cell6 9 cell6 8 cell6 7 cell6 6 cell6 5 cell6 4 cell6 3 cell6 2 cell6 1 cell6 0 9c 9d cell 7 voltage this is the voltage of cell7. reserved cell7 b cell7 a cell7 9 cell7 8 cell7 7 cell7 6 cell7 5 cell7 4 cell7 3 cell7 2 cell7 1 cell7 0 hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 ? 4095 gain ? senser ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- -
isl94202 25. registers: detailed (ram) fn8889 rev.2.00 page 85 of 89 mar 8, 2017 9e 9f cell 8 voltage this is the voltage of cell8. reserved cell8 b cell8 a cell8 9 cell8 8 cell8 7 cell8 6 cell8 5 cell8 4 cell8 3 cell8 2 cell8 1 cell8 0 a0 a1 internal temperature this is the voltage reported by the isl94202 internal temperatu re sensor. reserved itb ita it9 it8 it7 it6 it5 it4 it3 it2 it1 it0 a2 a3 external temperature 1 this is the voltage reported by an external thermistor divider on the xt1 pin. reserved xt1b xt1a xt19 xt18 xt17 xt16 xt15 xt14 xt13 xt12 xt11 xt10 a4 a5 external temperature 2 this is the voltage reported by an external thermistor divider on the xt2 pin. reserved xt2b xt2a xt29 xt28 xt27 xt26 xt25 xt24 xt23 xt22 xt21 xt20 a6 a7 vbatt voltage this is the voltage of pack. reserved vbb vba vb9 vb8 vb7 vb6 vb5 vb4 vb3 vb2 vb1 vb0 a8 a9 vrgo voltage this is the voltage of isl94202 2.5v regulator. reserved rgob rgoa rgo 9 rgo 8 rgo 7 rgo 6 rgo 5 rgo 4 rgo 3 rgo 2 rgo 1 rgo 0 table 25.18 ram register detail (monitored voltages)(continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210 hexvalue 10 1.8 8 ?? 4095 3 ? -------------------------------------------------------- - hexvalue 10 1.8 ? 4095 ----------------------------------------------- hexvalue 10 1.8 ? 4095 ----------------------------------------------- hexvalue 10 1.8 ? 4095 ----------------------------------------------- hexvalue 10 1.8 32 ?? 4095 ----------------------------------------------------------- - hexvalue 10 1.8 2 ?? 4095 -------------------------------------------------------- -
isl94202 25. registers: detailed (ram) fn8889 rev.2.00 page 86 of 89 mar 8, 2017 aa ab 14-bit adc voltage this is the calibrated voltage out of the isl94202 adc. in norm al scan mode, this value is not usable, because it cannot be associated with a specific monitored voltage. however, when the c takes over the scan operations, this value can be useful. this is a 2s complement number. reserved adc d adc c adc b adc a adc 9 adc 8 adc 7 adc 6 adc 5 adc 4 adc 3 adc 2 adc 1 adc 0 notes: 1. a 1 written to a control or configuration bit causes the action to be taken. a 1 read from a status bit indicates that t he condition exists. 2. reserved indicates that the bit or register is reserved for future expansion. when writing to ram addresses, write a reser ved bit with the value 0. do not write to reserved registers at addre sses 4ch through 4fh, 58h through 7fh, or ach through ffh. ignore reserved bits that are returned in a read operation. 3. the in_sleep bit is cleared on initial power up, by the chmon pin going high or by the ldmon pin going low. 4. when the automatic responses are enabled, these bits are auto matically set and reset by hardware when any conditions indicat e. when automatic responses are over-ridden, an external microcont roller i 2 c write operation controls the respective fet and a read of the register returns the current state of the fet drive outp ut circuit (though not the actual voltage at the output pin). 5. setting eeen to 0 prior to a read or write to the eeprom area results in a read or write to the shadow memory. setting eeen to 1 prior to a read or write from the eeprom area results in a read or write from the non-volatile array locations. 6. writes to eeprom registers require that the eeen bit be set t o 1 and all other bits in eeprom enable register set to 0 p rior to the write operation. 7. this bit is reset when the watchdog timer is active and expir es. 8. the memory is configured as eight pages of 16 bytes. the i 2 c can perform a page write to write all values on one page in a single cycle. 9. setting this bit to 1 disables all internal voltage and tem perature scans. when set to 1, the external c needs to proce ss all overvoltage, undervoltage, over-temp, under temp and all cell b alance operations. 10.short-circuit, open-wire, internal over temperature, ovlo an d uvlo faults, plus sleep, and fetsoff conditions override the cfet control bit and automatically force the appropriate power fets off. table 25.18 ram register detail (monitored voltages)(continued) bit/ addr f 7 e 6 d 5 c 4 b 3 a 2 9 1 8 0 76543210 if .. hexvalue 10 8191 ? hexvalue 10 16384 C ?? 1.8 ? 8191 -------------------------------------------------------------------------------------------- ? else hexvalue 10 1.8 ? 8191 -------------------------------------------- ?
isl94202 26. revision history fn8889 rev.2.00 page 87 of 89 mar 8, 2017 26. revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please vis it our website to make sure you h ave the latest revision. date revision change mar 7, 2017 fn8889.2 updated entire datasheet to new standards. updated applications section on page 1 added table #1.1 on page 4. dec 12, 2016 fn8889.1 ordering information table on page 4, updated note 1 to include tape and reel options and quantities. esd rating on page 8, human body model (tested per jesd22-a114f) changed from: 2kv to: 1.5kv oct 24, 2016 fn8889.0 initial release.
isl94202 27. package outline drawing fn8889 rev.2.00 page 88 of 89 mar 8, 2017 27. package outline drawing l48.6x6 48 lead thin quad flat no-lead plastic package rev 2, 7/14 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicate d. the pin #1 id entifier may be unless otherwise specified , tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metalliz ed terminal and is mea sured dim ensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 0.05 a b pin 1 index area (4x) 0.15 6 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 0.80 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ) ( 4. 40) (48x 0 . 20) (48x 0 . 65) (44 x 0.40) 0.05 m c 6.00 0.05 for the most recent package outline drawing, see l48.6x6
isl94202 28. about intersil fn8889 rev.2.00 page 89 of 89 mar 8, 2017 28. about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's products address some of the larg est markets within the industr ial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related documentation, an d related parts, see th e respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary . you may report errors or suggestions for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also ava ilable from our website at www.intersil.com/support . ? copyright intersil americas llc 2016-2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners.

▲Up To Search▲

Price & Availability of ISL94202EVKIT1Z

	To Download ISL94202EVKIT1Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .